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[RISC-V] Fix receiving of 2nd register in struct #86144
[RISC-V] Fix receiving of 2nd register in struct #86144
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Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch Issue DetailsPart of #84834.
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@t-mustafin Could you give examples (or tests) which this PR can fix? I just want to try and see emitted codes. Thank you. |
@clamp03 I got exception with this backtrace for helloworld.dll launch without output redirection:
G_M26687_IG01: ; offs=000000H, size=0088H, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG
800002B7 lui t0, -524288
FFF28293 addi t0, t0, -1
00B29293 slli t0, t0, 11
7FF28293 addi t0, t0, 2047
00B29293 slli t0, t0, 11
7FE28293 addi t0, t0, 2046
00B29293 slli t0, t0, 11
7B028293 addi t0, t0, 1968
00510133 add sp, sp, t0
00813023 sd fp, 0(sp)
00113423 sd ra, 8(sp)
00010413 addi fp, sp, 0
1E840293 addi t0, fp, 488
06400313 addi t1, zero, 100
0002B423 sd zero, 8(t0)
0002B023 sd zero, 0(t0)
FFF30313 addi t1, t1, -1
01028293 addi t0, t0, 16
FE0318E3 bne t1, zero, -16
0002B023 sd zero, 0(t0)
000010B7 lui ra, 1
84008093 addi ra, ra, -1984
008080B3 add ra, ra, fp
00A0B023 sd a0, 0(ra) ; ra is valid stack address here
00808093 addi ra, ra, 8
008080B3 add ra, ra, fp ; ra already has a valid address, addition fp to ra breaks ra.
00B0B023 sd a1, 0(ra) ; Segmentation fault is here. ra = 0x7fffff8748; sp = 0x3fffffbf80
000010B7 lui ra, 1
83008093 addi ra, ra, -2000
008080B3 add ra, ra, fp
00C0B023 sd a2, 0(ra) For output redirection case ( |
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Thank you!
I made a JIT tests launch with and without this change, but flaky
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IMO, below lines should be fixed too. Could you check? runtime/src/coreclr/jit/codegenriscv64.cpp Lines 7939 to 7940 in 5053c7c
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@clamp03 thanks for showing this, it has same logic. This paths work in rare case: more then 1024bytes for local variables && structs of size in range (XLEN, 2*XLEN] passing as arguments. I think it is the reason why test launches show no difference. |
@t-mustafin I found that
Then it can affect below parts in runtime/src/coreclr/jit/emitriscv64.cpp Lines 2636 to 2662 in 16fc92f
What I suggest are
@jakobbotsch Could you suggest better solutions for us? Thank you! + @t-mustafin Could you run jit-format for the commits? |
In general I would suggest replicating how arm64 codegen handles these cases. You can see that it forms the temporary register with the offset inside |
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Fixes output to console.
Part of #84834.
cc @alpencolt @gbalykov @clamp03