Skip to content

Commit

Permalink
added readme
Browse files Browse the repository at this point in the history
  • Loading branch information
dpiegdon committed Mar 23, 2019
1 parent 3f4619f commit f7b887e
Showing 1 changed file with 6 additions and 0 deletions.
6 changes: 6 additions & 0 deletions README.md
@@ -0,0 +1,6 @@
Rewrite of WS2812 fancy fader project in Verilog for Lattice HX1K FPGAs.

Purely done for training and out of curiosity.

Original version of fancy fader for ATTiny85:
https://github.com/dpiegdon/digispark-workbench/tree/master/projects/ws2812-fancy-fader

0 comments on commit f7b887e

Please sign in to comment.