Skip to content
View drichmond's full-sized avatar

Highlights

  • Pro
Block or Report

Block or report drichmond

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Pinned

  1. KastnerRG/riffa KastnerRG/riffa Public

    The RIFFA development repository

    Verilog 724 303

  2. Xilinx/PYNQ Xilinx/PYNQ Public

    Python Productivity for ZYNQ

    Jupyter Notebook 1.9k 801

  3. bespoke-silicon-group/bsg_manycore bespoke-silicon-group/bsg_manycore Public

    Tile based architecture designed for computing efficiency, scalability and generality

    SystemVerilog 212 56

  4. PYNQ-HLS PYNQ-HLS Public

    A Tutorial on Putting High-Level Synthesis cores in PYNQ

    Jupyter Notebook 99 25

  5. RISC-V-On-PYNQ RISC-V-On-PYNQ Public

    RISC-V Integration for PYNQ

    Tcl 163 53

  6. HOPS HOPS Public

    Synthesizable Higher-Order Functions (Patterns) for C++

    C++ 16