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llvm: Update baseline to 6aeea700df6f3f8db9e6a79be4aa593c6fcc7d18
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github-actions[bot] committed May 28, 2024
1 parent f42f8d3 commit 1298620
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Showing 3 changed files with 16 additions and 38 deletions.
2 changes: 1 addition & 1 deletion llvm/llvm-project
Submodule llvm-project updated 39 files
+109 −0 .github/workflows/restart-preempted-libcxx-jobs.yaml
+1 −1 clang/lib/CodeGen/CodeGenPGO.cpp
+7 −7 clang/lib/Serialization/ASTWriter.cpp
+8 −8 flang/module/cudadevice.f90
+36 −0 flang/test/Lower/CUDA/cuda-device-proc.cuf
+53 −50 llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+20 −0 llvm/lib/Target/RISCV/RISCVInstrInfo.td
+27 −8 llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
+23 −0 llvm/lib/Target/RISCV/RISCVPostRAExpandPseudoInsts.cpp
+77 −0 llvm/test/Analysis/ScalarEvolution/predicated-symbolic-max-backedge-taken-count.ll
+11 −11 llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
+4 −4 llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
+7 −7 llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll
+2 −2 llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll
+2 −2 llvm/test/CodeGen/RISCV/rv32xtheadbb.ll
+2 −2 llvm/test/CodeGen/RISCV/rv32zbb.ll
+20 −20 llvm/test/CodeGen/RISCV/rvv/active_lane_mask.ll
+2 −2 llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
+133 −142 llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
+10 −10 llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
+8 −8 llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
+40 −40 llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
+5 −5 llvm/test/CodeGen/RISCV/rvv/fixed-vectors-stepvector.ll
+25 −25 llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll
+4 −4 llvm/test/CodeGen/RISCV/tail-calls.ll
+13 −19 llvm/test/CodeGen/RISCV/unroll-loop-cse.ll
+0 −45 mlir/include/mlir/Analysis/DataFlow/IntegerRangeAnalysis.h
+8 −8 mlir/include/mlir/Dialect/Arith/IR/ArithOps.td
+6 −6 mlir/include/mlir/Dialect/GPU/IR/GPUOps.td
+1 −1 mlir/include/mlir/Dialect/Index/IR/IndexOps.td
+74 −1 mlir/include/mlir/Interfaces/InferIntRangeInterface.h
+36 −10 mlir/include/mlir/Interfaces/InferIntRangeInterface.td
+6 −2 mlir/include/mlir/Interfaces/Utils/InferIntRangeCommon.h
+14 −37 mlir/lib/Analysis/DataFlow/IntegerRangeAnalysis.cpp
+12 −6 mlir/lib/Dialect/Arith/IR/InferIntRangeInterfaceImpls.cpp
+48 −0 mlir/lib/Interfaces/InferIntRangeInterface.cpp
+1 −1 mlir/lib/Interfaces/Utils/InferIntRangeCommon.cpp
+19 −0 mlir/test/Dialect/Arith/int-range-interface.mlir
+5 −4 mlir/test/lib/Dialect/Test/TestOps.td
18 changes: 4 additions & 14 deletions result/rvv/2baa092f704376f3.S
View file
Original file line number Diff line number Diff line change
Expand Up @@ -15,32 +15,22 @@ func0000000000000014: # @func0000000000000014
func0000000000000004: # @func0000000000000004
addi sp, sp, -16
csrr a1, vlenb
slli a1, a1, 4
slli a1, a1, 3
sub sp, sp, a1
vsetivli zero, 16, e64, m8, ta, ma
vle64.v v24, (a0)
vfabs.v v24, v24
csrr a0, vlenb
sh3add a0, a0, sp
addi a0, a0, 16
vs8r.v v24, (a0) # Unknown-size Folded Spill
lui a0, %hi(.LCPI1_0)
addi a0, a0, %lo(.LCPI1_0)
vlse64.v v24, (a0), zero
vlse64.v v0, (a0), zero
addi a0, sp, 16
vs8r.v v24, (a0) # Unknown-size Folded Spill
vs8r.v v0, (a0) # Unknown-size Folded Spill
fli.d fa5, 1.0
csrr a0, vlenb
sh3add a0, a0, sp
addi a0, a0, 16
vl8r.v v24, (a0) # Unknown-size Folded Reload
vmfgt.vf v0, v24, fa5
addi a0, sp, 16
vl8r.v v24, (a0) # Unknown-size Folded Reload
vmerge.vvm v16, v24, v16, v0
vfmul.vv v8, v16, v8
csrr a0, vlenb
slli a0, a0, 4
add sp, sp, a0
sh3add sp, a0, sp
addi sp, sp, 16
ret
34 changes: 11 additions & 23 deletions result/rvv/f2735940afb56c81.S
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,48 +5,36 @@
func0000000000000000: # @func0000000000000000
addi sp, sp, -16
csrr a1, vlenb
slli a1, a1, 3
sh1add a1, a1, a1
slli a1, a1, 4
sub sp, sp, a1
vsetivli zero, 16, e64, m8, ta, ma
vle64.v v24, (a0)
csrr a0, vlenb
slli a0, a0, 4
add a0, a0, sp
sh3add a0, a0, sp
addi a0, a0, 16
vs8r.v v24, (a0) # Unknown-size Folded Spill
lui a0, %hi(.LCPI0_0)
addi a0, a0, %lo(.LCPI0_0)
vlse64.v v24, (a0), zero
vlse64.v v0, (a0), zero
lui a0, %hi(.LCPI0_1)
addi a0, a0, %lo(.LCPI0_1)
vlse64.v v0, (a0), zero
vlse64.v v24, (a0), zero
addi a0, sp, 16
vs8r.v v0, (a0) # Unknown-size Folded Spill
vs8r.v v24, (a0) # Unknown-size Folded Spill
csrr a0, vlenb
sh3add a0, a0, sp
addi a0, a0, 16
vs8r.v v8, (a0) # Unknown-size Folded Spill
csrr a0, vlenb
slli a0, a0, 4
add a0, a0, sp
addi a0, a0, 16
vl8r.v v0, (a0) # Unknown-size Folded Reload
vfmacc.vv v24, v16, v0
vl8r.v v24, (a0) # Unknown-size Folded Reload
vfmacc.vv v0, v16, v24
addi a0, sp, 16
vl8r.v v8, (a0) # Unknown-size Folded Reload
vfmacc.vv v8, v16, v24
vl8r.v v24, (a0) # Unknown-size Folded Reload
vfmacc.vv v24, v16, v0
fli.d fa5, 1.0
vfmv.v.f v0, fa5
vfmacc.vv v0, v16, v8
csrr a0, vlenb
sh3add a0, a0, sp
addi a0, a0, 16
vl8r.v v8, (a0) # Unknown-size Folded Reload
vfmacc.vv v0, v16, v24
vfdiv.vv v8, v8, v0
csrr a0, vlenb
slli a0, a0, 3
sh1add a0, a0, a0
slli a0, a0, 4
add sp, sp, a0
addi sp, sp, 16
ret

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