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llvm: Update baseline to f68548135b8f9a02beac842646ab89bcaad9d400
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github-actions[bot] committed May 22, 2024
1 parent f2b0d1a commit 2a1a31e
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Showing 4 changed files with 14 additions and 14 deletions.
2 changes: 1 addition & 1 deletion llvm/llvm-project
Submodule llvm-project updated 31 files
+4 −0 clang/lib/AST/Interp/EvaluationResult.cpp
+5 −1 clang/lib/AST/Interp/Interp.h
+0 −3 clang/lib/AST/Interp/Pointer.h
+4 −0 clang/test/AST/Interp/arrays.cpp
+14 −0 clang/test/AST/Interp/unions.cpp
+0 −1 flang/include/flang/Optimizer/HLFIR/Passes.h
+1 −2 flang/include/flang/Optimizer/HLFIR/Passes.td
+2 −1 flang/include/flang/Tools/CLOptions.inc
+2 −7 flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp
+7 −0 flang/test/Driver/mlir-pass-pipeline.f90
+8 −1 flang/test/Fir/basic-program.fir
+0 −25 llvm/include/llvm/Analysis/LoopInfo.h
+0 −6 llvm/include/llvm/Transforms/Utils/LoopUtils.h
+12 −10 llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+0 −65 llvm/lib/Transforms/Utils/LoopUtils.cpp
+37 −19 llvm/test/Analysis/LoopAccessAnalysis/depend_diff_types.ll
+26 −11 llvm/test/Analysis/LoopAccessAnalysis/forward-loop-independent.ll
+27 −3 llvm/test/Analysis/LoopAccessAnalysis/pr64637.ll
+227 −119 llvm/test/Analysis/LoopAccessAnalysis/stride-access-dependence.ll
+1 −1 llvm/test/CodeGen/AArch64/arm64-vhadd.ll
+0 −0 llvm/test/MC/AArch64/SVE/condition-codes.s
+2 −2 llvm/test/MC/AArch64/SVE/sqdecd-diagnostics.s
+16 −16 llvm/test/MC/AArch64/SVE/sqincp-diagnostics.s
+0 −129 llvm/test/Transforms/IndVarSimplify/pr51735-1.ll
+0 −128 llvm/test/Transforms/IndVarSimplify/pr51735-2.ll
+0 −131 llvm/test/Transforms/IndVarSimplify/pr51735-3.ll
+0 −104 llvm/test/Transforms/IndVarSimplify/pr51735.ll
+4 −4 llvm/test/Transforms/Util/add-TLI-mappings.ll
+1 −0 llvm/utils/gn/secondary/clang/lib/StaticAnalyzer/Checkers/BUILD.gn
+77 −0 mlir/lib/Bindings/Python/IRAttributes.cpp
+82 −0 mlir/test/python/ir/array_attributes.py
10 changes: 5 additions & 5 deletions result/rvv/07185607a67a1e6e.S
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Original file line number Diff line number Diff line change
@@ -1,10 +1,10 @@
func0000000000000029: # @func0000000000000029
vsetivli zero, 4, e64, m2, ta, ma
vsra.vi v8, v8, 4
vadd.vi v10, v8, 1
vadd.vi v8, v8, 1
li a0, 63
vsrl.vx v10, v10, a0
csrwi vxrm, 0
vaadd.vv v8, v8, v10
vsll.vi v8, v8, 4
vsrl.vx v10, v8, a0
vadd.vv v8, v8, v10
vsll.vi v8, v8, 3
vand.vi v8, v8, -16
ret
10 changes: 5 additions & 5 deletions result/rvv/b45aaad152bc6ef3.S
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Original file line number Diff line number Diff line change
Expand Up @@ -2,10 +2,10 @@ func0000000000000029: # @func0000000000000029
vsetivli zero, 4, e64, m2, ta, ma
vsub.vv v8, v8, v10
vsra.vi v8, v8, 4
vadd.vi v10, v8, 1
vadd.vi v8, v8, 1
li a0, 63
vsrl.vx v10, v10, a0
csrwi vxrm, 0
vaadd.vv v8, v8, v10
vsll.vi v8, v8, 4
vsrl.vx v10, v8, a0
vadd.vv v8, v8, v10
vsll.vi v8, v8, 3
vand.vi v8, v8, -16
ret
6 changes: 3 additions & 3 deletions result/rvv/f4fdffdea80e871a.S
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Original file line number Diff line number Diff line change
Expand Up @@ -17,7 +17,7 @@ func0000000000000009: # @func0000000000000009
vsra.vi v10, v8, 2
li a0, 63
vsrl.vx v8, v8, a0
csrwi vxrm, 2
vaadd.vv v8, v10, v8
vsll.vi v8, v8, 3
vadd.vv v8, v10, v8
vsll.vi v8, v8, 2
vand.vi v8, v8, -8
ret

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