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Merge branch 'master' of http://github.com/dyninst/dyninst into att_s…
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…yntax_merge
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John Detter committed Dec 19, 2016
2 parents 6de9520 + c09b5ba commit 7c0cfd4
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Showing 55 changed files with 4,844 additions and 1,892 deletions.
5 changes: 4 additions & 1 deletion cmake/packages.cmake
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Expand Up @@ -20,7 +20,10 @@ if (UNIX)

add_library(libelf_imp SHARED IMPORTED)
set_property(TARGET libelf_imp
PROPERTY IMPORTED_LOCATION ${LIBELF_LIBRARIES})
PROPERTY IMPORTED_LOCATION ${LIBELF_LIBRARIES})
if(NOT LIBELF_FOUND)
add_dependencies(libelf_imp LibElf)
endif()

find_package (LibDwarf)

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4 changes: 2 additions & 2 deletions common/doc/manual_frontpage.tex
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Expand Up @@ -42,9 +42,9 @@
% };

\node [anchor=west,font=\sffamily] (rel1) at ($(origin)+(0.75in,-5.0in)$)
{\fontsize{24}{32}\selectfont 9.2 Release};
{\fontsize{24}{32}\selectfont 9.3 Release};
\node [anchor=west,font=\sffamily] (rel2) at ($(rel1.west)+(0in,-32pt)$)
{\fontsize{24}{32}\selectfont June 2016};
{\fontsize{24}{32}\selectfont December 2016};

% Contact information
% \matrix (UWaddress) [%
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18 changes: 16 additions & 2 deletions common/h/dyn_regs.h
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Expand Up @@ -99,11 +99,14 @@ namespace Dyninst
static MachRegister getSyscallNumberReg(Dyninst::Architecture arch);
static MachRegister getSyscallNumberOReg(Dyninst::Architecture arch);
static MachRegister getSyscallReturnValueReg(Dyninst::Architecture arch);
static MachRegister getZeroFlag(Dyninst::Architecture arch);

bool isPC() const;
bool isFramePointer() const;
bool isStackPointer() const;
bool isSyscallNumberReg() const;
bool isSyscallReturnValueReg() const;
bool isFlag() const;

void getROSERegister(int &c, int &n, int &p);

Expand Down Expand Up @@ -274,8 +277,8 @@ namespace Dyninst
DEF_REGISTER(k5, 0x05 | OCT | KMASK| Arch_x86, "x86");
DEF_REGISTER(k6, 0x06 | OCT | KMASK| Arch_x86, "x86");
DEF_REGISTER(k7, 0x07 | OCT | KMASK| Arch_x86, "x86");

DEF_REGISTER(xmm0, 0x00 | OCT | XMM | Arch_x86, "x86");
DEF_REGISTER(xmm0, 0x00 | OCT | XMM | Arch_x86, "x86");
DEF_REGISTER(xmm1, 0x01 | OCT | XMM | Arch_x86, "x86");
DEF_REGISTER(xmm2, 0x02 | OCT | XMM | Arch_x86, "x86");
DEF_REGISTER(xmm3, 0x03 | OCT | XMM | Arch_x86, "x86");
Expand Down Expand Up @@ -1074,10 +1077,12 @@ namespace Dyninst
//arch reg cat:GPR alias&subrange reg ID
const signed int GPR = 0x00010000;
const signed int FPR = 0x00020000;
const signed int FLAG = 0x00030000;
const signed int FSR = 0x00040000;
const signed int SPR = 0x00080000;
const signed int SYSREG = 0x00100000;

const signed int BIT = 0x00008000;
const signed int B_REG = 0x00000100; //8bit byte reg
const signed int W_REG = 0x00000300; //16bit half-wor reg
const signed int D_REG = 0x00000f00; //32bit single-word reg
Expand Down Expand Up @@ -1366,11 +1371,20 @@ namespace Dyninst

//special registers
//PC is not writable in aarch64
const signed int N_FLAG = 31;
const signed int Z_FLAG = 30;
const signed int C_FLAG = 29;
const signed int V_FLAG = 28;

DEF_REGISTER(sp, 0 | FULL |SPR | Arch_aarch64, "aarch64");
DEF_REGISTER(wsp, 0 | D_REG |SPR | Arch_aarch64, "aarch64");
DEF_REGISTER(pc, 1 | FULL |SPR | Arch_aarch64, "aarch64");
DEF_REGISTER(pstate, 2 | D_REG |SPR | Arch_aarch64, "aarch64");
DEF_REGISTER(xzr, 3 | FULL |SPR | Arch_aarch64, "aarch64");
DEF_REGISTER(n, N_FLAG | BIT |FLAG| Arch_aarch64, "aarch64");
DEF_REGISTER(z, Z_FLAG | BIT |FLAG| Arch_aarch64, "aarch64");
DEF_REGISTER(c, C_FLAG | BIT |FLAG| Arch_aarch64, "aarch64");
DEF_REGISTER(v, V_FLAG | BIT |FLAG| Arch_aarch64, "aarch64");
DEF_REGISTER(wzr, 3 | D_REG |SPR | Arch_aarch64, "aarch64");
DEF_REGISTER(fpcr, 4 | D_REG |SPR | Arch_aarch64, "aarch64");
DEF_REGISTER(fpsr, 5 | D_REG |SPR | Arch_aarch64, "aarch64");
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146 changes: 115 additions & 31 deletions common/src/dyn_regs.C
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Expand Up @@ -202,11 +202,13 @@ unsigned int MachRegister::size() const {
return 0;
}
}
else if((reg & 0x00ff0000) == aarch64::GPR || (reg & 0x00ff0000) == aarch64::SPR || (reg & 0x00ff0000) == aarch64::SYSREG)
else if((reg & 0x00ff0000) == aarch64::GPR || (reg & 0x00ff0000) == aarch64::SPR ||
(reg & 0x00ff0000) == aarch64::SYSREG || (reg & 0x00ff0000) == aarch64::FLAG)
switch(reg & 0x0000ff00)
{
case aarch64::FULL : return 8;
case aarch64::D_REG: return 4;
case aarch64::BIT: return 0;
default: return 0;
}
else
Expand Down Expand Up @@ -418,6 +420,25 @@ MachRegister MachRegister::getArchRegFromAbstractReg(MachRegister abstract,
return Dyninst::InvalidReg;
}

MachRegister MachRegister::getZeroFlag(Dyninst::Architecture arch)
{
switch (arch)
{
case Arch_x86:
return x86::zf;
case Arch_x86_64:
return x86_64::zf;
case Arch_aarch64:
return aarch64::z;
case Arch_aarch32:
assert(0);
case Arch_none:
return InvalidReg;
}
return InvalidReg;
}


bool MachRegister::isPC() const
{
return (*this == x86_64::rip || *this == x86::eip ||
Expand Down Expand Up @@ -457,6 +478,23 @@ bool MachRegister::isSyscallReturnValueReg() const
);
}

bool MachRegister::isFlag() const
{
int regC = regClass();
switch (getArchitecture())
{
case Arch_x86:
return regC == x86::FLAG;
case Arch_x86_64:
return regC == x86_64::FLAG;
case Arch_aarch64:
return regC == aarch64::FLAG;
default:
assert(!"Not implemented!");
}
return false;
}

COMMON_EXPORT bool Dyninst::isSegmentRegister(int regClass)
{
return 0 != (regClass & x86::SEG);
Expand Down Expand Up @@ -808,36 +846,82 @@ void MachRegister::getROSERegister(int &c, int &n, int &p)
return;
}
break;
case Arch_aarch64:
{
switch(category) {
case aarch64::GPR: {
c = armv8_regclass_gpr;
if(baseID == aarch64::xzr || baseID == aarch64::wzr)
n = armv8_gpr_zr;
else {
int regnum = baseID - aarch64::x0;
n = armv8_gpr_r0 + regnum;
}
}
break;
case aarch64::SPR: {
n = 0;
if(baseID == (aarch64::pstate & 0xFF)) {
c = armv8_regclass_pstate;
p = armv8_pstatefield_nzcv;
} else if(baseID == (aarch64::pc & 0xFF)) {
c = armv8_regclass_pc;
} else if(baseID == (aarch64::sp & 0xFF) || baseID == (aarch64::wsp & 0xFF)) {
c = armv8_regclass_sp;
}
}
break;
default:assert(!"unknown register type!");
break;
}
return;
}
case Arch_aarch64: {
p = 0;
switch (category) {
case aarch64::GPR: {
c = armv8_regclass_gpr;
int regnum = baseID - (aarch64::x0 & 0xFF);
n = armv8_gpr_r0 + regnum;
}
break;
case aarch64::SPR: {
n = 0;
if (baseID == (aarch64::pstate & 0xFF)) {
c = armv8_regclass_pstate;
} else if(baseID == (aarch64::xzr & 0xFF) || baseID == (aarch64::wzr & 0xFF)) {
c = armv8_regclass_gpr;
n = armv8_gpr_zr;
} else if (baseID == (aarch64::pc & 0xFF)) {
c = armv8_regclass_pc;
} else if (baseID == (aarch64::sp & 0xFF) || baseID == (aarch64::wsp & 0xFF)) {
c = armv8_regclass_sp;
}
}
break;
case aarch64::FPR: {
c = armv8_regclass_simd_fpr;

int firstRegId;
switch(reg & 0xFF00) {
case aarch64::Q_REG: firstRegId = (aarch64::q0 & 0xFF);
break;
case aarch64::HQ_REG: firstRegId = (aarch64::hq0 & 0xFF);
p = 64;
break;
case aarch64::FULL: firstRegId = (aarch64::d0 & 0xFF);
break;
case aarch64::D_REG: firstRegId = (aarch64::s0 & 0xFF);
break;
case aarch64::W_REG: firstRegId = (aarch64::h0 & 0xFF);
break;
case aarch64::B_REG: firstRegId = (aarch64::b0 & 0xFF);
break;
default:assert(!"invalid register subcategory for ARM64!");
break;
}
n = armv8_simdfpr_v0 + (baseID - firstRegId);
}
break;
case aarch64::FLAG: {
c = armv8_regclass_pstate;
n = 0;
switch (baseID) {
case aarch64::N_FLAG:
p = armv8_pstatefield_n;
break;
case aarch64::Z_FLAG:
p = armv8_pstatefield_z;
break;
case aarch64::V_FLAG:
p = armv8_pstatefield_v;
break;
case aarch64::C_FLAG:
p = armv8_pstatefield_c;
break;
default:
assert(!"unknown flag type!");
break;
}
}
break;
default:
assert(!"unknown register type!");
break;
}
return;
}

break;
default:
c = x86_regclass_unknown;
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Binary file modified dataflowAPI/doc/dataflowAPI.pdf
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6 changes: 3 additions & 3 deletions dataflowAPI/h/SymEval.h
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Expand Up @@ -96,7 +96,7 @@ struct Variable {
}
friend std::ostream& operator<<(std::ostream& stream, const Variable& c)
{
stream << c.format() << std::endl;
stream << c.format();
return stream;
}

Expand Down Expand Up @@ -129,7 +129,7 @@ struct Constant {
}
friend std::ostream& operator<<(std::ostream& stream, const Constant& c)
{
stream << c.format() << std::endl;
stream << c.format();
return stream;
}

Expand Down Expand Up @@ -290,7 +290,7 @@ DATAFLOW_EXPORT const std::string format() const {
};
friend std::ostream& operator<<(std::ostream& stream, const ROSEOperation& c)
{
stream << c.format() << std::endl;
stream << c.format();
return stream;
}

Expand Down
13 changes: 13 additions & 0 deletions dataflowAPI/rose/semantics/BaseSemantics2.C
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Expand Up @@ -691,6 +691,19 @@ Dispatcher::read(SgAsmExpression *e, size_t value_nbits/*=0*/, size_t addr_nbits
SgAsmExpression *lhs = product->get_lhs();
SgAsmExpression *rhs = product->get_rhs();
retval = operators->unsignedMultiply(read(lhs, lhs->get_nBits()), read(rhs, rhs->get_nBits()));
} else if (SgAsmBinaryLsl *lshift = isSgAsmBinaryLsl(e)) {
SgAsmExpression *lhs = lshift->get_lhs();
SgAsmExpression *rhs = lshift->get_rhs();
size_t nbits = std::max(lhs->get_nBits(), rhs->get_nBits());
retval = operators->shiftLeft(read(lhs, lhs->get_nBits()), read(rhs, rhs->get_nBits()));
} else if(SgAsmBinaryAsr *asr = isSgAsmBinaryAsr(e)) {
SgAsmExpression *lhs = asr->get_lhs();
SgAsmExpression *rhs = asr->get_rhs();
retval = operators->shiftRightArithmetic(read(lhs, lhs->get_nBits()), read(rhs, rhs->get_nBits()));
} else if(SgAsmBinaryLsr *lsr = isSgAsmBinaryLsr(e)) {
SgAsmExpression *lhs = lsr->get_lhs();
SgAsmExpression *rhs = lsr->get_rhs();
retval = operators->shiftRight(read(lhs, lhs->get_nBits()), read(rhs, rhs->get_nBits()));
} else {
ASSERT_not_implemented(e->class_name());
}
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