Updated invalid instruction detection code for SIMD scalar three-same

and SIMD scalar two-register miscellaneous instruction categories.
dyninst · Dec 19, 2016 · d62aa74 · d62aa74
1 parent fea0fdb
commit d62aa74
Showing 1 changed file with 22 additions and 8 deletions.
diff --git a/instructionAPI/src/InstructionDecoder-aarch64.C b/instructionAPI/src/InstructionDecoder-aarch64.C
@@ -480,13 +480,24 @@ namespace Dyninst {
 		int S = opcode & 0x1;
 
 		if(opcode != 0x1 && opcode != 0x5 && ((opcode >> 3) & 0x3) != 0x3) {
-		    if(((opcode >> 2) & 0x2) == 0x2 && S == 0 && size != 0x3)
-			isValid = false;
-		    else if(opcode == 0x16 && (size == 0 || size == 0x3))
-			isValid = false;
-		    else if(opcode != 0x16 && size != 0x3)
-			isValid = false;
+		    if(opcode == 0x16) {
+			if(size == 0 || size == 0x3)
+			    isValid = false;
+		    } else {
+			if(((opcode >> 2) & 0x2) == 0x2) {
+			    if(S == 0 && size != 0x3)
+				isValid = false;
+			} else if(size != 0x3) {
+			    isValid = false;
+			}
+		    }
 		}
+	    } else if(IS_INSN_SCALAR_2REG_MISC(insn)) {
+		int opcode = field<12, 16>(insn);
+
+		if(((opcode == 0x14 || opcode == 0x12) && size == 0x3) ||
+		    (opcode >= 0x8 && opcode <= 0xB && size != 0x3))
+		    isValid = false;
 	    }
         }
 
@@ -644,12 +655,15 @@ namespace Dyninst {
                         }
                     }
                     else {
-                        switch (_szField) {
+                        entryID op = insn_in_progress->getOperation().operationID;
+
+			switch (_szField) {
                             case 0x0:
                                 reg = aarch64::s0;
+				if(op == aarch64_op_fcvtxn_advsimd)
+				    isValid = false;
                                 break;
                             case 0x1: {
-                                entryID op = insn_in_progress->getOperation().operationID;
                                 reg = (op == aarch64_op_fcvtxn_advsimd) ? aarch64::s0 : aarch64::d0;
                             }
                                 break;