Issue #249 (Reserved size value for some vector register instructions is

ignored) Check for invalid 'S' and 'size' field values for SIMD scalar three-same instructions
dyninst · Dec 19, 2016 · fea0fdb · fea0fdb
1 parent 7c0cfd4
commit fea0fdb
Showing 1 changed file with 15 additions and 3 deletions.
diff --git a/instructionAPI/src/InstructionDecoder-aarch64.C b/instructionAPI/src/InstructionDecoder-aarch64.C
@@ -470,12 +470,24 @@ namespace Dyninst {
             size = field<startBit, endBit>(insn);
 
             entryID insnID = insn_in_progress->getOperation().operationID;
+
             if((insnID == aarch64_op_pmull_advsimd && (size == 0x1 || size == 0x2)) ||
                ((IS_INSN_SIMD_3DIFF(insn) || IS_INSN_SCALAR_3DIFF(insn)) && size == 0x3) ||
-               ((insnID == aarch64_op_sqdmull_advsimd_vec || insnID == aarch64_op_sqdmlal_advsimd_vec || insnID == aarch64_op_sqdmlsl_advsimd_vec)
-                 && size == 0)) {
+               ((insnID == aarch64_op_sqdmull_advsimd_vec || insnID == aarch64_op_sqdmlal_advsimd_vec || insnID == aarch64_op_sqdmlsl_advsimd_vec) && size == 0)) {
                 isValid = false;
-            }
+            } else if(IS_INSN_SCALAR_3SAME(insn)) {
+		int opcode = field<11, 15>(insn);
+		int S = opcode & 0x1;
+
+		if(opcode != 0x1 && opcode != 0x5 && ((opcode >> 3) & 0x3) != 0x3) {
+		    if(((opcode >> 2) & 0x2) == 0x2 && S == 0 && size != 0x3)
+			isValid = false;
+		    else if(opcode == 0x16 && (size == 0 || size == 0x3))
+			isValid = false;
+		    else if(opcode != 0x16 && size != 0x3)
+			isValid = false;
+		}
+	    }
         }
 
         Expression::Ptr InstructionDecoder_aarch64::makeRdExpr() {