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[TargetLowering] StringRefize asm constraint getters.
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There is some functional change here because it changes target code from
atoi(3) to StringRef::getAsInteger which has error checking. For valid
constraints there should be no difference.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241411 91177308-0d34-0410-b5e6-96231b3b80d8
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@d0k
d0k committed Jul 5, 2015
1 parent c6e8efa commit adc0236
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Showing 26 changed files with 81 additions and 111 deletions.
7 changes: 3 additions & 4 deletions include/llvm/Target/TargetLowering.h
View file
Expand Up @@ -2679,7 +2679,7 @@ class TargetLowering : public TargetLoweringBase {
SelectionDAG *DAG = nullptr) const;

/// Given a constraint, return the type of constraint it is for this target.
virtual ConstraintType getConstraintType(const std::string &Constraint) const;
virtual ConstraintType getConstraintType(StringRef Constraint) const;

/// Given a physical register constraint (e.g. {edx}), return the register
/// number and the register class for the register.
Expand All @@ -2692,10 +2692,9 @@ class TargetLowering : public TargetLoweringBase {
/// returns a register number of 0 and a null register class pointer.
virtual std::pair<unsigned, const TargetRegisterClass *>
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
const std::string &Constraint, MVT VT) const;
StringRef Constraint, MVT VT) const;

virtual unsigned
getInlineAsmMemConstraint(const std::string &ConstraintCode) const {
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const {
if (ConstraintCode == "i")
return InlineAsm::Constraint_i;
else if (ConstraintCode == "m")
Expand Down
7 changes: 3 additions & 4 deletions lib/CodeGen/SelectionDAG/TargetLowering.cpp
View file
Expand Up @@ -2105,9 +2105,8 @@ PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
// Inline Assembler Implementation Methods
//===----------------------------------------------------------------------===//


TargetLowering::ConstraintType
TargetLowering::getConstraintType(const std::string &Constraint) const {
TargetLowering::getConstraintType(StringRef Constraint) const {
unsigned S = Constraint.size();

if (S == 1) {
Expand Down Expand Up @@ -2140,7 +2139,7 @@ TargetLowering::getConstraintType(const std::string &Constraint) const {
}

if (S > 1 && Constraint[0] == '{' && Constraint[S-1] == '}') {
if (S == 8 && !Constraint.compare(1, 6, "memory", 6)) // "{memory}"
if (S == 8 && Constraint.substr(1, 6) == "memory") // "{memory}"
return C_Memory;
return C_Register;
}
Expand Down Expand Up @@ -2227,7 +2226,7 @@ void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,

std::pair<unsigned, const TargetRegisterClass *>
TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *RI,
const std::string &Constraint,
StringRef Constraint,
MVT VT) const {
if (Constraint.empty() || Constraint[0] != '{')
return std::make_pair(0u, static_cast<TargetRegisterClass*>(nullptr));
Expand Down
12 changes: 5 additions & 7 deletions lib/Target/AArch64/AArch64ISelLowering.cpp
View file
Expand Up @@ -4232,7 +4232,7 @@ bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
/// getConstraintType - Given a constraint letter, return the type of
/// constraint it is for this target.
AArch64TargetLowering::ConstraintType
AArch64TargetLowering::getConstraintType(const std::string &Constraint) const {
AArch64TargetLowering::getConstraintType(StringRef Constraint) const {
if (Constraint.size() == 1) {
switch (Constraint[0]) {
default:
Expand Down Expand Up @@ -4283,8 +4283,7 @@ AArch64TargetLowering::getSingleConstraintMatchWeight(

std::pair<unsigned, const TargetRegisterClass *>
AArch64TargetLowering::getRegForInlineAsmConstraint(
const TargetRegisterInfo *TRI, const std::string &Constraint,
MVT VT) const {
const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
if (Constraint.size() == 1) {
switch (Constraint[0]) {
case 'r':
Expand Down Expand Up @@ -4320,10 +4319,9 @@ AArch64TargetLowering::getRegForInlineAsmConstraint(
unsigned Size = Constraint.size();
if ((Size == 4 || Size == 5) && Constraint[0] == '{' &&
tolower(Constraint[1]) == 'v' && Constraint[Size - 1] == '}') {
const std::string Reg =
std::string(&Constraint[2], &Constraint[Size - 1]);
int RegNo = atoi(Reg.c_str());
if (RegNo >= 0 && RegNo <= 31) {
int RegNo;
bool Failed = Constraint.slice(2, Size - 1).getAsInteger(10, RegNo);
if (!Failed && RegNo >= 0 && RegNo <= 31) {
// v0 - v31 are aliases of q0 - q31.
// By default we'll emit v0-v31 for this unless there's a modifier where
// we'll emit the correct register as well.
Expand Down
9 changes: 3 additions & 6 deletions lib/Target/AArch64/AArch64ISelLowering.h
View file
Expand Up @@ -471,8 +471,7 @@ class AArch64TargetLowering : public TargetLowering {
std::vector<SDNode *> *Created) const override;
bool combineRepeatedFPDivisors(unsigned NumUsers) const override;

ConstraintType
getConstraintType(const std::string &Constraint) const override;
ConstraintType getConstraintType(StringRef Constraint) const override;
unsigned getRegisterByName(const char* RegName, EVT VT) const override;

/// Examine constraint string and operand type and determine a weight value.
Expand All @@ -483,14 +482,12 @@ class AArch64TargetLowering : public TargetLowering {

std::pair<unsigned, const TargetRegisterClass *>
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
const std::string &Constraint,
MVT VT) const override;
StringRef Constraint, MVT VT) const override;
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
std::vector<SDValue> &Ops,
SelectionDAG &DAG) const override;

unsigned getInlineAsmMemConstraint(
const std::string &ConstraintCode) const override {
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
if (ConstraintCode == "Q")
return InlineAsm::Constraint_Q;
// FIXME: clang has code for 'Ump', 'Utf', 'Usa', and 'Ush' but these are
Expand Down
3 changes: 1 addition & 2 deletions lib/Target/AMDGPU/SIISelLowering.cpp
View file
Expand Up @@ -2212,9 +2212,8 @@ SDValue SITargetLowering::CreateLiveInRegister(SelectionDAG &DAG,

std::pair<unsigned, const TargetRegisterClass *>
SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
const std::string &Constraint_,
StringRef Constraint,
MVT VT) const {
StringRef Constraint(Constraint_);
if (Constraint == "r") {
switch(VT.SimpleTy) {
default: llvm_unreachable("Unhandled type for 'r' inline asm constraint");
Expand Down
6 changes: 3 additions & 3 deletions lib/Target/AMDGPU/SIISelLowering.h
View file
Expand Up @@ -114,9 +114,9 @@ class SITargetLowering : public AMDGPUTargetLowering {
SDLoc DL,
SDValue Ptr) const;

std::pair<unsigned, const TargetRegisterClass *> getRegForInlineAsmConstraint(
const TargetRegisterInfo *TRI,
const std::string &Constraint, MVT VT) const override;
std::pair<unsigned, const TargetRegisterClass *>
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
StringRef Constraint, MVT VT) const override;
SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, SDLoc DL, SDValue V) const;
};

Expand Down
8 changes: 3 additions & 5 deletions lib/Target/ARM/ARMISelLowering.cpp
View file
Expand Up @@ -10664,7 +10664,7 @@ bool ARMTargetLowering::ExpandInlineAsm(CallInst *CI) const {
/// getConstraintType - Given a constraint letter, return the type of
/// constraint it is for this target.
ARMTargetLowering::ConstraintType
ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
ARMTargetLowering::getConstraintType(StringRef Constraint) const {
if (Constraint.size() == 1) {
switch (Constraint[0]) {
default: break;
Expand Down Expand Up @@ -10723,10 +10723,8 @@ ARMTargetLowering::getSingleConstraintMatchWeight(
}

typedef std::pair<unsigned, const TargetRegisterClass*> RCPair;
RCPair
ARMTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
const std::string &Constraint,
MVT VT) const {
RCPair ARMTargetLowering::getRegForInlineAsmConstraint(
const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
if (Constraint.size() == 1) {
// GCC ARM Constraint Letters
switch (Constraint[0]) {
Expand Down
10 changes: 4 additions & 6 deletions lib/Target/ARM/ARMISelLowering.h
View file
Expand Up @@ -324,8 +324,7 @@ namespace llvm {

bool ExpandInlineAsm(CallInst *CI) const override;

ConstraintType
getConstraintType(const std::string &Constraint) const override;
ConstraintType getConstraintType(StringRef Constraint) const override;

/// Examine constraint string and operand type and determine a weight value.
/// The operand object must already have been set up with the operand type.
Expand All @@ -334,8 +333,7 @@ namespace llvm {

std::pair<unsigned, const TargetRegisterClass *>
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
const std::string &Constraint,
MVT VT) const override;
StringRef Constraint, MVT VT) const override;

/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
/// vector. If it is invalid, don't add anything to Ops. If hasMemory is
Expand All @@ -345,8 +343,8 @@ namespace llvm {
std::vector<SDValue> &Ops,
SelectionDAG &DAG) const override;

unsigned getInlineAsmMemConstraint(
const std::string &ConstraintCode) const override {
unsigned
getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
if (ConstraintCode == "Q")
return InlineAsm::Constraint_Q;
else if (ConstraintCode.size() == 2) {
Expand Down
3 changes: 1 addition & 2 deletions lib/Target/Hexagon/HexagonISelLowering.cpp
View file
Expand Up @@ -2338,8 +2338,7 @@ HexagonTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,

std::pair<unsigned, const TargetRegisterClass *>
HexagonTargetLowering::getRegForInlineAsmConstraint(
const TargetRegisterInfo *TRI, const std::string &Constraint,
MVT VT) const {
const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
if (Constraint.size() == 1) {
switch (Constraint[0]) {
case 'r': // R0-R31
Expand Down
7 changes: 3 additions & 4 deletions lib/Target/Hexagon/HexagonISelLowering.h
View file
Expand Up @@ -179,11 +179,10 @@ bool isPositiveHalfWord(SDNode *N);

std::pair<unsigned, const TargetRegisterClass *>
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
const std::string &Constraint,
MVT VT) const override;
StringRef Constraint, MVT VT) const override;

unsigned getInlineAsmMemConstraint(
const std::string &ConstraintCode) const override {
unsigned
getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
if (ConstraintCode == "o")
return InlineAsm::Constraint_o;
else if (ConstraintCode == "v")
Expand Down
5 changes: 2 additions & 3 deletions lib/Target/MSP430/MSP430ISelLowering.cpp
View file
Expand Up @@ -213,7 +213,7 @@ SDValue MSP430TargetLowering::LowerOperation(SDValue Op,
/// getConstraintType - Given a constraint letter, return the type of
/// constraint it is for this target.
TargetLowering::ConstraintType
MSP430TargetLowering::getConstraintType(const std::string &Constraint) const {
MSP430TargetLowering::getConstraintType(StringRef Constraint) const {
if (Constraint.size() == 1) {
switch (Constraint[0]) {
case 'r':
Expand All @@ -227,8 +227,7 @@ MSP430TargetLowering::getConstraintType(const std::string &Constraint) const {

std::pair<unsigned, const TargetRegisterClass *>
MSP430TargetLowering::getRegForInlineAsmConstraint(
const TargetRegisterInfo *TRI, const std::string &Constraint,
MVT VT) const {
const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
if (Constraint.size() == 1) {
// GCC Constraint Letters
switch (Constraint[0]) {
Expand Down
5 changes: 2 additions & 3 deletions lib/Target/MSP430/MSP430ISelLowering.h
View file
Expand Up @@ -96,11 +96,10 @@ namespace llvm {
SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;

TargetLowering::ConstraintType
getConstraintType(const std::string &Constraint) const override;
getConstraintType(StringRef Constraint) const override;
std::pair<unsigned, const TargetRegisterClass *>
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
const std::string &Constraint,
MVT VT) const override;
StringRef Constraint, MVT VT) const override;

/// isTruncateFree - Return true if it's free to truncate a value of type
/// Ty1 to type Ty2. e.g. On msp430 it's free to truncate a i16 value in
Expand Down
18 changes: 8 additions & 10 deletions lib/Target/Mips/MipsISelLowering.cpp
View file
Expand Up @@ -3198,9 +3198,8 @@ MipsTargetLowering::LowerReturn(SDValue Chain,

/// getConstraintType - Given a constraint letter, return the type of
/// constraint it is for this target.
MipsTargetLowering::ConstraintType MipsTargetLowering::
getConstraintType(const std::string &Constraint) const
{
MipsTargetLowering::ConstraintType
MipsTargetLowering::getConstraintType(StringRef Constraint) const {
// Mips specific constraints
// GCC config/mips/constraints.md
//
Expand Down Expand Up @@ -3290,17 +3289,16 @@ MipsTargetLowering::getSingleConstraintMatchWeight(
/// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag
/// that is returned indicates whether parsing was successful. The second flag
/// is true if the numeric part exists.
static std::pair<bool, bool>
parsePhysicalReg(StringRef C, std::string &Prefix,
unsigned long long &Reg) {
static std::pair<bool, bool> parsePhysicalReg(StringRef C, StringRef &Prefix,
unsigned long long &Reg) {
if (C.front() != '{' || C.back() != '}')
return std::make_pair(false, false);

// Search for the first numeric character.
StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1;
I = std::find_if(B, E, std::ptr_fun(isdigit));

Prefix.assign(B, I - B);
Prefix = StringRef(B, I - B);

// The second flag is set to false if no numeric characters were found.
if (I == E)
Expand All @@ -3316,7 +3314,7 @@ parseRegForInlineAsmConstraint(StringRef C, MVT VT) const {
const TargetRegisterInfo *TRI =
Subtarget.getRegisterInfo();
const TargetRegisterClass *RC;
std::string Prefix;
StringRef Prefix;
unsigned long long Reg;

std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg);
Expand All @@ -3332,7 +3330,7 @@ parseRegForInlineAsmConstraint(StringRef C, MVT VT) const {
RC = TRI->getRegClass(Prefix == "hi" ?
Mips::HI32RegClassID : Mips::LO32RegClassID);
return std::make_pair(*(RC->begin()), RC);
} else if (Prefix.compare(0, 4, "$msa") == 0) {
} else if (Prefix.startswith("$msa")) {
// Parse $msa(ir|csr|access|save|modify|request|map|unmap)

// No numeric characters follow the name.
Expand Down Expand Up @@ -3390,7 +3388,7 @@ parseRegForInlineAsmConstraint(StringRef C, MVT VT) const {
/// pointer.
std::pair<unsigned, const TargetRegisterClass *>
MipsTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
const std::string &Constraint,
StringRef Constraint,
MVT VT) const {
if (Constraint.size() == 1) {
switch (Constraint[0]) {
Expand Down
10 changes: 4 additions & 6 deletions lib/Target/Mips/MipsISelLowering.h
View file
Expand Up @@ -478,8 +478,7 @@ namespace llvm {
bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override;

// Inline asm support
ConstraintType
getConstraintType(const std::string &Constraint) const override;
ConstraintType getConstraintType(StringRef Constraint) const override;

/// Examine constraint string and operand type and determine a weight value.
/// The operand object must already have been set up with the operand type.
Expand All @@ -493,8 +492,7 @@ namespace llvm {

std::pair<unsigned, const TargetRegisterClass *>
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
const std::string &Constraint,
MVT VT) const override;
StringRef Constraint, MVT VT) const override;

/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
/// vector. If it is invalid, don't add anything to Ops. If hasMemory is
Expand All @@ -505,8 +503,8 @@ namespace llvm {
std::vector<SDValue> &Ops,
SelectionDAG &DAG) const override;

unsigned getInlineAsmMemConstraint(
const std::string &ConstraintCode) const override {
unsigned
getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
if (ConstraintCode == "R")
return InlineAsm::Constraint_R;
else if (ConstraintCode == "ZC")
Expand Down
4 changes: 2 additions & 2 deletions lib/Target/NVPTX/NVPTXISelLowering.cpp
View file
Expand Up @@ -3772,7 +3772,7 @@ bool NVPTXTargetLowering::isLegalAddressingMode(const AddrMode &AM,
/// getConstraintType - Given a constraint letter, return the type of
/// constraint it is for this target.
NVPTXTargetLowering::ConstraintType
NVPTXTargetLowering::getConstraintType(const std::string &Constraint) const {
NVPTXTargetLowering::getConstraintType(StringRef Constraint) const {
if (Constraint.size() == 1) {
switch (Constraint[0]) {
default:
Expand All @@ -3794,7 +3794,7 @@ NVPTXTargetLowering::getConstraintType(const std::string &Constraint) const {

std::pair<unsigned, const TargetRegisterClass *>
NVPTXTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
const std::string &Constraint,
StringRef Constraint,
MVT VT) const {
if (Constraint.size() == 1) {
switch (Constraint[0]) {
Expand Down
6 changes: 2 additions & 4 deletions lib/Target/NVPTX/NVPTXISelLowering.h
View file
Expand Up @@ -468,12 +468,10 @@ class NVPTXTargetLowering : public TargetLowering {
return MVT::i1;
}

ConstraintType
getConstraintType(const std::string &Constraint) const override;
ConstraintType getConstraintType(StringRef Constraint) const override;
std::pair<unsigned, const TargetRegisterClass *>
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
const std::string &Constraint,
MVT VT) const override;
StringRef Constraint, MVT VT) const override;

SDValue LowerFormalArguments(
SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
Expand Down
4 changes: 2 additions & 2 deletions lib/Target/PowerPC/PPCISelLowering.cpp
View file
Expand Up @@ -10691,7 +10691,7 @@ unsigned PPCTargetLowering::getPrefLoopAlignment(MachineLoop *ML) const {
/// getConstraintType - Given a constraint, return the type of
/// constraint it is for this target.
PPCTargetLowering::ConstraintType
PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
PPCTargetLowering::getConstraintType(StringRef Constraint) const {
if (Constraint.size() == 1) {
switch (Constraint[0]) {
default: break;
Expand Down Expand Up @@ -10776,7 +10776,7 @@ PPCTargetLowering::getSingleConstraintMatchWeight(

std::pair<unsigned, const TargetRegisterClass *>
PPCTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
const std::string &Constraint,
StringRef Constraint,
MVT VT) const {
if (Constraint.size() == 1) {
// GCC RS6000 Constraint Letters
Expand Down

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