platform: Add RISC-V architecture with VisionFive

Add RISC-V architecture and StarFive JH71x0-based boards VisionFive and VisionFive 2. Signed-off-by: Daniel Bovensiepen <oss@bovi.li> Signed-off-by: Zhu Jia Xing <jiaxing.zhu@siemens.com>
eclipse · Sep 21, 2023 · 0df2e0f · 0df2e0f
1 parent 7c2ba41
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Showing 12 changed files with 659 additions and 2 deletions.
diff --git a/CMakeLists.txt b/CMakeLists.txt
@@ -192,10 +192,12 @@ elseif (DETECTED_ARCH MATCHES "mips")
   set (MIPSPLAT ON)
 elseif (DETECTED_ARCH STREQUAL "MOCK")
   set (MOCKPLAT ON)
+elseif (DETECTED_ARCH STREQUAL "riscv64")
+  set (RISCVPLAT ON)
 elseif (DETECTED_ARCH STREQUAL "PERIPHERALMAN")
   set (PERIPHERALMAN ON)
 else ()
-  message (FATAL_ERROR "Only x86, arm, mips, PERIPHERALMAN and mock platforms currently supported")
+  message (FATAL_ERROR "Only x86, arm, mips, riscv, PERIPHERALMAN and mock platforms currently supported")
 endif()
 
 if (BUILDSWIGPYTHON OR BUILDTESTS)

diff --git a/README.md b/README.md
@@ -73,6 +73,10 @@ JSON platform
 ----
 * [Platform loading](../master/docs/jsonplatform.md)
 
+RISC-V
+----
+* [VisionFive](../master/docs/visionfive.md)
+
 Installing on your board
 ========================
 

diff --git a/api/mraa/types.h b/api/mraa/types.h
@@ -70,6 +70,8 @@ typedef enum {
     MRAA_INTEL_ILK = 25,            /**< Intel Learning Kit */
     MRAA_SIEMENS_IOT2050 = 26,      /**< Siemens IOT2050 board */
     MRAA_RADXA_ROCK_3C = 27,        /**< Radxa ROCK 3 Model C */
+    MRAA_VISIONFIVE = 28,           /**< StarFive VisionFive board */
+
     // USB platform extenders start at 256
     MRAA_FTDI_FT4222 = 256,         /**< FTDI FT4222 USB to i2c bridge */
 

diff --git a/api/mraa/types.hpp b/api/mraa/types.hpp
@@ -64,6 +64,7 @@ typedef enum {
     INTEL_UPXTREME = 24,        /**< The UPXTREME Board */
     SIEMENS_IOT2050 = 26,      /**< Siemens IOT2050 board */
     RADXA_ROCK_3C = 27,        /**< Radxa ROCK 3 Model C */
+    VISIONFIVE = 28,           /**< StarFive VisionFive board */
 
     FTDI_FT4222 = 256,         /**< FTDI FT4222 USB to i2c bridge */
 

diff --git a/docs/visionfive.md b/docs/visionfive.md
@@ -0,0 +1,108 @@
+VisionFive
+============
+
+The VisionFive is based on the StarFive JH71x0 system on a chip family, which
+includes an U74 Dual-Core RISC-V processor and ships with 2/4/8 gigabytes of RAM.
+
+Revision Support
+----------------
+
+VisionFive (JH7100) and VisionFive 2 (JH7110).
+
+Interface notes
+---------------
+
+PWM is currently not supported.
+
+Pin Mapping
+-----------
+
+The pin mapping refers to the VisionFive model:
+
+| MRAA Number | Physical Pin | Function |
+|-------------|--------------|----------|
+| 1           | P1-01        | 3V3 VCC  |
+| 2           | P1-02        | 5V VCC   |
+| 3           | P1-03        | I2C SDA  |
+| 4           | P1-04        | 5V VCC   |
+| 5           | P1-05        | I2C SCL  |
+| 6           | P1-06        | GND      |
+| 7           | P1-07        | GPIO(46) |
+| 8           | P1-08        | UART TX  |
+| 9           | P1-09        | GND      |
+| 10          | P1-10        | UART RX  |
+| 11          | P1-11        | GPIO(44) |
+| 12          | P1-12        | GPIO(45) |
+| 13          | P1-13        | GPIO(22) |
+| 14          | P1-14        | GND      |
+| 15          | P1-15        | GPIO(20) |
+| 16          | P1-16        | GPIO(21) |
+| 17          | P1-17        | 3V3 VCC  |
+| 18          | P1-18        | GPIO(19) |
+| 19          | P1-19        | SPI MOSI |
+| 20          | P1-20        | GND      |
+| 21          | P1-21        | SPI MISO |
+| 22          | P1-22        | GPIO(17) |
+| 23          | P1-23        | SPI SCL  |
+| 24          | P1-24        | SPI CS0  |
+| 25          | P1-25        | GND      |
+| 26          | P1-26        | SPI CS1  |
+| 27          | P1-27        | GPIO(9)  |
+| 28          | P1-28        | GPIO(10) |
+| 29          | P1-29        | GPIO(8)  |
+| 30          | P1-30        | GND      |
+| 31          | P1-31        | GPIO(6)  |
+| 32          | P1-32        | PWM0     |
+| 33          | P1-33        | PWM1     |
+| 34          | P1-34        | GND      |
+| 35          | P1-35        | GPIO(3)  |
+| 36          | P1-36        | GPIO(4)  |
+| 37          | P1-37        | GPIO(1)  |
+| 38          | P1-38        | GPIO(2)  |
+| 39          | P1-39        | GND      |
+| 40          | P1-40        | GPIO(0)  |
+
+The following pin mapping refers to the VisionFive 2 model:
+
+| MRAA Number | Physical Pin | Function |
+|-------------|--------------|----------|
+| 1           | P1-01        | 3V3 VCC  |
+| 2           | P1-02        | 5V VCC   |
+| 3           | P1-03        | I2C SDA  |
+| 4           | P1-04        | 5V VCC   |
+| 5           | P1-05        | I2C SCL  |
+| 6           | P1-06        | GND      |
+| 7           | P1-07        | GPIO(55) |
+| 8           | P1-08        | UART TX  |
+| 9           | P1-09        | GND      |
+| 10          | P1-10        | UART RX  |
+| 11          | P1-11        | GPIO(42) |
+| 12          | P1-12        | GPIO(38) |
+| 13          | P1-13        | GPIO(43) |
+| 14          | P1-14        | GND      |
+| 15          | P1-15        | GPIO(47) |
+| 16          | P1-16        | GPIO(54) |
+| 17          | P1-17        | 3V3 VCC  |
+| 18          | P1-18        | GPIO(51) |
+| 19          | P1-19        | SPI MOSI |
+| 20          | P1-20        | GND      |
+| 21          | P1-21        | SPI MISO |
+| 22          | P1-22        | GPIO(50) |
+| 23          | P1-23        | SPI SCL  |
+| 24          | P1-24        | SPI CS0  |
+| 25          | P1-25        | GND      |
+| 26          | P1-26        | GPIO(56) |
+| 27          | P1-27        | GPIO(45) |
+| 28          | P1-28        | GPIO(40) |
+| 29          | P1-29        | GPIO(37) |
+| 30          | P1-30        | GND      |
+| 31          | P1-31        | GPIO(39) |
+| 32          | P1-32        | PWM0     |
+| 33          | P1-33        | PWM1     |
+| 34          | P1-34        | GND      |
+| 35          | P1-35        | GPIO(63) |
+| 36          | P1-36        | GPIO(36) |
+| 37          | P1-37        | GPIO(60) |
+| 38          | P1-38        | GPIO(61) |
+| 39          | P1-39        | GND      |
+| 40          | P1-40        | GPIO(44) |
diff --git a/include/mraa_internal.h b/include/mraa_internal.h
@@ -61,6 +61,13 @@ mraa_platform_t mraa_mips_platform();
  * @return mraa_platform_t of the init'ed platform
  */
 mraa_platform_t mraa_mock_platform();
+
+/**
+ * runtime detect running risc-v platforms
+ *
+ * @return mraa_platform_t of the init'ed platform
+ */
+mraa_platform_t mraa_riscv_platform();
 
 /**
  * runtime detect iio subsystem

diff --git a/include/riscv/visionfive.h b/include/riscv/visionfive.h
@@ -0,0 +1,24 @@
+/*
+ * Author: Daniel Bovensiepen <oss@bovi.li>
+ * Author: Zhu Jia Xing <jiaxing.zhu@siemens.com>
+ * Copyright (c) 2022 Siemens Ltd. China.
+ *
+ * SPDX-License-Identifier: MIT
+ */
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "mraa_internal.h"
+
+#define MRAA_VISIONFIVE_PINCOUNT 41
+
+mraa_board_t *
+        mraa_visionfive();
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt
@@ -130,6 +130,11 @@ set (mraa_LIB_MOCK_SRCS_NOAUTO
   ${PROJECT_SOURCE_DIR}/src/mock/mock_board_uart.c
 )
 
+set (mraa_LIB_RISCV_SRCS_NOAUTO
+  ${PROJECT_SOURCE_DIR}/src/riscv/riscv.c
+  ${PROJECT_SOURCE_DIR}/src/riscv/visionfive.c
+)
+
 set (mraa_LIB_PERIPHERALMAN_SRCS_NOAUTO
   ${PROJECT_SOURCE_DIR}/src/peripheralman/peripheralman.c
 )
@@ -170,6 +175,11 @@ if (MOCKPLAT)
   endif ()
 endif()
 
+if (RISCVPLAT)
+  add_subdirectory(riscv)
+  set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -DRISCVPLAT=1")
+endif()
+
 if (PERIPHERALMAN)
   set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -DPERIPHERALMAN=1")
 

diff --git a/src/mraa.c b/src/mraa.c
@@ -153,14 +153,17 @@ imraa_init()
         // Use runtime ARM platform detection
         platform_type = mraa_arm_platform();
 #elif defined(MIPSPLAT)
-        // Use runtime ARM platform detection
+        // Use runtime MIPS platform detection
         platform_type = mraa_mips_platform();
 #elif defined(MOCKPLAT)
         // Use mock platform
         platform_type = mraa_mock_platform();
 #elif defined(PERIPHERALMAN)
         // Use peripheralmanager
         platform_type = mraa_peripheralman_platform();
+#elif defined(RISCVPLAT)
+        // Use runtime RISC-V platform detection
+        platform_type = mraa_riscv_platform();
 #else
 #error mraa_ARCH NOTHING
 #endif

diff --git a/src/riscv/CMakeLists.txt b/src/riscv/CMakeLists.txt
@@ -0,0 +1,3 @@
+message (INFO " - Adding RISC-V platforms")
+set (mraa_LIB_PLAT_SRCS_NOAUTO ${mraa_LIB_SRCS_NOAUTO}
+     ${mraa_LIB_RISCV_SRCS_NOAUTO} PARENT_SCOPE)
diff --git a/src/riscv/riscv.c b/src/riscv/riscv.c
@@ -0,0 +1,33 @@
+/*
+ * Author: Daniel Bovensiepen <oss@bovi.li>
+ * Author: Zhu Jia Xing <jiaxing.zhu@siemens.com>
+ * Copyright (c) 2022 Siemens Ltd. China.
+ *
+ * SPDX-License-Identifier: MIT
+ */
+
+#include <stdlib.h>
+#include <string.h>
+
+#include "riscv/visionfive.h"
+#include "mraa_internal.h"
+
+mraa_platform_t
+mraa_riscv_platform()
+{
+    mraa_platform_t platform_type = MRAA_UNKNOWN_PLATFORM;
+    if (mraa_file_contains("/proc/device-tree/compatible", "visionfive")) {
+        platform_type = MRAA_VISIONFIVE;
+    }
+
+    switch (platform_type) {
+        case MRAA_VISIONFIVE:
+            plat = mraa_visionfive();
+            break;
+
+        default:
+            plat = NULL;
+            syslog(LOG_ERR, "Unknown Platform, currently not supported by MRAA");
+    }
+    return platform_type;
+}