AArch64: Vector bitwise AND operation

This commit adds AArch64 implementation for vector bitwise AND operation. This implementation is for the following data type- - VectorInt8 Signed-off-by: Md. Alvee Noor <mnoor@unb.ca>
eclipse · May 7, 2021 · 0d7fc8c · 0d7fc8c
1 parent d96f2b3
commit 0d7fc8c
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Showing 5 changed files with 20 additions and 1 deletion.
diff --git a/compiler/aarch64/codegen/ARM64Debug.cpp b/compiler/aarch64/codegen/ARM64Debug.cpp
@@ -512,6 +512,7 @@ static const char *opCodeToNameMap[] =
    "vfmul2d",
    "vfdiv4s",
    "vfdiv2d",
+   "vand16b",
    "nop",
    "proc",
    "fence",

diff --git a/compiler/aarch64/codegen/BinaryEvaluator.cpp b/compiler/aarch64/codegen/BinaryEvaluator.cpp
@@ -371,6 +371,22 @@ OMR::ARM64::TreeEvaluator::vdivEvaluator(TR::Node *node, TR::CodeGenerator *cg)
    return inlineVectorBinaryOp(node, cg, divOp);
    }
 
+TR::Register *
+OMR::ARM64::TreeEvaluator::vandEvaluator(TR::Node *node, TR::CodeGenerator *cg)
+   {
+   TR::InstOpCode::Mnemonic andOp;
+   switch(node->getDataType())
+      {
+      case TR::VectorInt8:
+         andOp = TR::InstOpCode::vand16b;
+         break;
+      default:
+         TR_ASSERT(false, "unrecognized vector type %s\n", node->getDataType().toString());
+         return NULL;
+      }
+   return inlineVectorBinaryOp(node, cg, andOp);
+   }
+
 // Multiply a register by a 32-bit constant
 static void mulConstant32(TR::Node *node, TR::Register *treg, TR::Register *sreg, int32_t value, TR::CodeGenerator *cg)
    {

diff --git a/compiler/aarch64/codegen/OMRInstOpCodeEnum.hpp b/compiler/aarch64/codegen/OMRInstOpCodeEnum.hpp
@@ -493,6 +493,7 @@
 		vfmul2d,                                                  	/* 0x6E60DC00	FMUL      	 */
 		vfdiv4s,                                                  	/* 0x6E20FC00	FDIV      	 */
 		vfdiv2d,                                                  	/* 0x6E60FC00	FDIV      	 */
+		vand16b,                                                  	/* 0x4E201C00	AND      	 */
 /* Hint instructions */
 		nop,                                                    	/* 0xD503201F   NOP          */
 /* Internal OpCodes */

diff --git a/compiler/aarch64/codegen/OMRTreeEvaluatorTable.hpp b/compiler/aarch64/codegen/OMRTreeEvaluatorTable.hpp
@@ -471,7 +471,7 @@
 #define _vmulEvaluator TR::TreeEvaluator::vmulEvaluator
 #define _vdivEvaluator TR::TreeEvaluator::vdivEvaluator
 #define _vremEvaluator TR::TreeEvaluator::unImpOpEvaluator
-#define _vandEvaluator TR::TreeEvaluator::unImpOpEvaluator
+#define _vandEvaluator TR::TreeEvaluator::vandEvaluator
 #define _vorEvaluator TR::TreeEvaluator::unImpOpEvaluator
 #define _vxorEvaluator TR::TreeEvaluator::unImpOpEvaluator
 #define _vshlEvaluator TR::TreeEvaluator::unImpOpEvaluator

diff --git a/compiler/aarch64/codegen/OpBinary.cpp b/compiler/aarch64/codegen/OpBinary.cpp
@@ -492,6 +492,7 @@ const OMR::ARM64::InstOpCode::OpCodeBinaryEntry OMR::ARM64::InstOpCode::binaryEn
 		0x6E60DC00,	/* FMUL      	vfmul2d	 */
 		0x6E20FC00,	/* FDIV      	vfdiv4s	 */
 		0x6E60FC00,	/* FDIV      	vfdiv2d	 */
+		0x4E201C00,	/* AND      	vand16b	 */
 	/* Hint instructions */
 		0xD503201F,	/* NOP          nop      */
 };