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Fold assignToHPR as false
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Now that all three HPR related transformations have been deprecated
we can start cleaning up all HPR related APIs. We start with the
`assignToHPR` API which was the primary interface between global and
local RA.

This API determined whether a particular virtual register is to be
assigned to an HPR the first time the register becomes alive, or
whether when generating an instruction using such a register needs
to be upgraded to an equivalent HPR instruction.

We fold this API to always return false and all the code that
follows.

Signed-off-by: Filip Jeremic <fjeremic@ca.ibm.com>
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fjeremic committed Mar 9, 2019
1 parent 0cfbe8c commit 253bf1e
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Showing 8 changed files with 8 additions and 296 deletions.
33 changes: 1 addition & 32 deletions compiler/z/codegen/BinaryEvaluator.cpp
View file
Expand Up @@ -1387,29 +1387,7 @@ genericIntShift(TR::Node * node, TR::CodeGenerator * cg, TR::InstOpCode::Mnemoni
{
if (trgReg != srcReg && canUseAltShiftOp )
{
if (cg->supportsHighWordFacility() && srcReg->assignToHPR() &&
(altShiftOp == TR::InstOpCode::SLLK || altShiftOp == TR::InstOpCode::SRLK ))
{
if (altShiftOp == TR::InstOpCode::SLLK)
{
if (trgReg->assignToHPR())
altShiftOp = TR::InstOpCode::SLLHH;
else
altShiftOp = TR::InstOpCode::SLLLH;
}
else
{
if (trgReg->assignToHPR())
altShiftOp = TR::InstOpCode::SRLHH;
else
altShiftOp = TR::InstOpCode::SRLLH;
}
generateExtendedHighWordInstruction(node, cg, altShiftOp, trgReg, srcReg, shiftAmount);
}
else
{
generateRSInstruction(cg, altShiftOp, node, trgReg, srcReg, shiftAmount);
}
generateRSInstruction(cg, altShiftOp, node, trgReg, srcReg, shiftAmount);
}
else
{
Expand Down Expand Up @@ -1714,15 +1692,6 @@ genericRotateAndInsertHelper(TR::Node * node, TR::CodeGenerator * cg)
secondChild->getOpCode().isLoadConst() &&
firstChild->getSecondChild()->getOpCode().isLoadConst())
{
// if GRA had decided to assign HPR to these nodes, we cannot use RISBG because they are 64-bit
// instructions
if (cg->supportsHighWordFacility() &&
firstChild->getFirstChild()->getRegister() &&
firstChild->getFirstChild()->getRegister()->assignToHPR())
{
return NULL;
}

uint64_t value = 0;

// Mask
Expand Down
20 changes: 0 additions & 20 deletions compiler/z/codegen/OMRInstruction.cpp
View file
Expand Up @@ -1469,8 +1469,6 @@ OMR::Z::Instruction::assignOrderedRegisters(TR_RegisterKinds kindToBeAssigned)
if (!_targetReg[i]->getRegisterPair())
continue;

if (self()->cg()->supportsHighWordFacility())
_targetReg[i]->setAssignToHPR(false);
TR::Register *virtReg=_targetReg[i];
_targetReg[i] = self()->assignRegisterNoDependencies(virtReg);
_targetReg[i]->block();
Expand All @@ -1497,8 +1495,6 @@ OMR::Z::Instruction::assignOrderedRegisters(TR_RegisterKinds kindToBeAssigned)
if (!_sourceReg[i]->getRegisterPair())
continue;

if (self()->cg()->supportsHighWordFacility())
(_sourceReg[i])->setAssignToHPR(false);
(_sourceReg[i]) = self()->assignRegisterNoDependencies(_sourceReg[i]);
(_sourceReg[i])->block();

Expand All @@ -1517,22 +1513,6 @@ OMR::Z::Instruction::assignOrderedRegisters(TR_RegisterKinds kindToBeAssigned)

registerOperandNum = (_targetReg < _sourceReg) ? i+1 : _sourceRegSize+i+1;

if (self()->cg()->supportsHighWordFacility())
{
if ((self()->getOpCodeValue() == TR::InstOpCode::RISBLG || self()->getOpCodeValue() == TR::InstOpCode::RISBHG) &&
((TR::S390RIEInstruction *)self())->getExtendedHighWordOpCode().getOpCodeValue() != TR::InstOpCode::BAD)
{
if (((TR::S390RIEInstruction *)self())->getExtendedHighWordOpCode().isOperandHW(registerOperandNum))
_targetReg[i]->setAssignToHPR(true);
else
_targetReg[i]->setAssignToHPR(false);
}
else if (_opcode.isOperandHW(registerOperandNum))
_targetReg[i]->setAssignToHPR(true);
else
_targetReg[i]->setAssignToHPR(false);
}

if (_targetReg[i]->is64BitReg() && _targetReg[i]->getRealRegister() == NULL &&
_targetReg[i]->getKind() != TR_FPR && _targetReg[i]->getKind() != TR_VRF)
{
Expand Down
66 changes: 6 additions & 60 deletions compiler/z/codegen/OMRMachine.cpp
View file
Expand Up @@ -1193,32 +1193,8 @@ OMR::Z::Machine::assignBestRegisterSingle(TR::Register *targetRegister,
{
appendInst = currInst->getPrev();
}
//for 32-bit Registers, we need to make sure that the register is in the correct low/high word
if (assignedRegister->isLowWordRegister() && targetRegister->assignToHPR())
{
// need to find a free HPR and move assignedRegister there
TR::RealRegister * assignedHighWordRegister = NULL;

if ((assignedHighWordRegister = self()->findBestFreeRegister(currInst, kindOfRegister, targetRegister, availRegMask)) == NULL)
{
//assignedRegister->block();
assignedHighWordRegister = self()->freeBestRegister(currInst, targetRegister, kindOfRegister, availRegMask);
//assignedRegister->unblock();
}

TR::Instruction * cursor = generateExtendedHighWordInstruction(currInst->getNode(), self()->cg(), TR::InstOpCode::LLHFR, assignedRegister, assignedHighWordRegister, 0, appendInst);

self()->addToUpgradedBlockedList(assignedRegister) ?
assignedRegister->setState(TR::RealRegister::Blocked) :
assignedRegister->setState(TR::RealRegister::Free);
targetRegister->setAssignedRegister(assignedHighWordRegister);
assignedHighWordRegister->setAssignedRegister(targetRegister);
assignedHighWordRegister->setState(TR::RealRegister::Assigned);
assignedRegister->setAssignedRegister(NULL);
assignedRegister = assignedHighWordRegister;
self()->cg()->traceRAInstruction(cursor);
}
else if (assignedRegister->isHighWordRegister() && targetRegister->assignToGPR())

if (assignedRegister->isHighWordRegister() && targetRegister->assignToGPR())
{
// special case for RISBG, we can change the rotate amount to shuffle low word/ high word
if (currInst->getOpCodeValue() == TR::InstOpCode::RISBG || currInst->getOpCodeValue() == TR::InstOpCode::RISBGN)
Expand Down Expand Up @@ -2757,7 +2733,7 @@ OMR::Z::Machine::findBestFreeRegister(TR::Instruction *currentInstruction,
TR::RealRegister * candidate = NULL;
if (preference != 0 && (prefRegMask & availRegMask) && _registerFile[preference] != NULL)
{
if (virtualReg->assignToHPR() || needsHighWord)
if (needsHighWord)
candidate = _registerFile[preference]->getHighWordRegister();
else
candidate = _registerFile[preference]->getLowWordRegister();
Expand Down Expand Up @@ -2874,7 +2850,7 @@ OMR::Z::Machine::findBestFreeRegister(TR::Instruction *currentInstruction,
}
else
{
if (virtualReg->assignToHPR() || needsHighWord)
if (needsHighWord)
{
candidate = _registerFile[i]->getHighWordRegister();
tRegMask = candidate->getRealRegisterMask();
Expand Down Expand Up @@ -3183,33 +3159,7 @@ OMR::Z::Machine::freeBestRegister(TR::Instruction * currentInstruction, TR::Regi
{
TR::RealRegister * realRegHW = realReg->getHighWordRegister();

if (virtReg->assignToHPR())
{
if (realRegHW->getState() == TR::RealRegister::Assigned)
{
TR::Register * associatedVirtual = realRegHW->getAssignedRegister();

if ((!iInterfere && i==preference && pref_favored) || (realReg->getState() == TR::RealRegister::Free))
{
if (numCandidates == 0)
{
candidates[0] = associatedVirtual;
}
else
{
tempReg = candidates[0];
candidates[0] = associatedVirtual;
candidates[numCandidates] = tempReg;
}
}
else
{
candidates[numCandidates] = associatedVirtual;
}
numCandidates++;
}
}
else if (virtReg->assignToGPR())
if (virtReg->assignToGPR())
{
if (realReg->getState() == TR::RealRegister::Assigned)
{
Expand Down Expand Up @@ -3372,10 +3322,6 @@ OMR::Z::Machine::freeBestRegister(TR::Instruction * currentInstruction, TR::Regi
self()->cg()->traceRegisterAssignment("HW RA: freeBestReg Spill %R for fullsize reg: %R ", best->getHighWordRegister(), virtReg);
self()->spillRegister(currentInstruction, best->getHighWordRegister()->getAssignedRegister());
}
else if (virtReg->assignToHPR())
{
best = best->getHighWordRegister();
}
else if ((rk != TR_FPR && rk != TR_VRF) && (virtReg->is64BitReg() || virtReg->assignToGPR()))
{
best = best->getLowWordRegister();
Expand Down Expand Up @@ -3779,7 +3725,7 @@ OMR::Z::Machine::reverseSpillState(TR::Instruction *currentInstruction,
dataSize = TR::Compiler->om.sizeofReferenceAddress();
opCode = TR::InstOpCode::getStoreOpCode();

if (spilledRegister->assignToHPR() || targetRegister->isHighWordRegister())
if (targetRegister->isHighWordRegister())
{
//dataSize = 4;
opCode = TR::InstOpCode::STFH;
Expand Down
8 changes: 1 addition & 7 deletions compiler/z/codegen/OMRRegister.cpp
View file
Expand Up @@ -79,16 +79,10 @@ OMR::Z::Register::setPlaceholderReg()
OMR::Register::setPlaceholderReg();
}

bool
OMR::Z::Register::assignToHPR()
{
return (!(self()->is64BitReg()) && _flags.testAny(AssignToHPR));
}

bool
OMR::Z::Register::assignToGPR()
{
return (!(self()->is64BitReg()) && !_flags.testAny(AssignToHPR));
return !(self()->is64BitReg());
}

ncount_t
Expand Down
3 changes: 0 additions & 3 deletions compiler/z/codegen/OMRRegister.hpp
View file
Expand Up @@ -88,8 +88,6 @@ class OMR_EXTENSIBLE Register: public OMR::Register
bool is64BitReg();
void setIs64BitReg(bool b = true);

bool assignToHPR();
void setAssignToHPR(bool b = true) {_flags.set(AssignToHPR, b);}
bool assignToGPR();

bool isSpilledToHPR() {return (_flags.testAny(SpilledToHPR));}
Expand Down Expand Up @@ -136,7 +134,6 @@ class OMR_EXTENSIBLE Register: public OMR::Register
{
IsUsedInMemRef = 0x0800, // 390 cannot associate GPR0 to regs used in memrefs
Is64Bit = 0x0002, // 390 flag indicates that this Register contained a 64-bit value
AssignToHPR = 0x0004, // 390 flag indicates that this virtual register needs to be assigned to an HPR
SpilledToHPR = 0x4000, // 390 flag indicates that this virtual register is spilled to
DependencySet = 0x0200, // 390 flag, post dependancy was assigned

Expand Down
3 changes: 0 additions & 3 deletions compiler/z/codegen/OMRRegisterDependency.cpp
View file
Expand Up @@ -695,10 +695,8 @@ TR_S390RegisterDependencyGroup::checkRegisterPairSufficiencyAndHPRAssignment(TR:
virtRegI->setIs64BitReg(true);
}

virtRegI->setAssignToHPR(false);
if (TR::RealRegister::isHPR(realRegI))
{
virtRegI->setAssignToHPR(true);
cg->maskAvailableHPRSpillMask(~(machine->getRealRegister(realRegI)->getRealRegisterMask()));
}
else if (TR::RealRegister::isGPR(realRegI) && virtRegI->is64BitReg())
Expand Down Expand Up @@ -1509,7 +1507,6 @@ TR_S390RegisterDependencyGroup::assignRegisters(TR::Instruction *currentInstru

if(virtReg->isUsedInMemRef())
{
virtReg->setAssignToHPR(false);
uint32_t availRegMask =~TR::RealRegister::GPR0Mask;

// No bookkeeping on assignment call as we do bookkeeping at end of this method
Expand Down
17 changes: 0 additions & 17 deletions compiler/z/codegen/OMRTreeEvaluator.cpp
View file
Expand Up @@ -787,11 +787,6 @@ generateS390ImmOp(TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic memOp, TR::N
// LL: If Golden Eagle - can use Add Immediate with max 32-bit value.
ei_immOp = TR::InstOpCode::AFI;
}
if (targetRegister != NULL && targetRegister->assignToHPR())
{
immOp = TR::InstOpCode::BAD;
ei_immOp = TR::InstOpCode::AIH;
}
break;
case TR::InstOpCode::AG:
if (value == 0) return cursor;
Expand Down Expand Up @@ -854,11 +849,6 @@ generateS390ImmOp(TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic memOp, TR::N
// LL: If Golden Eagle - can use Compare Immediate with max 32-bit value.
ei_immOp = TR::InstOpCode::CFI;
}
if (targetRegister != NULL && targetRegister->assignToHPR())
{
immOp = TR::InstOpCode::BAD;
ei_immOp = TR::InstOpCode::CIH;
}
break;

case TR::InstOpCode::CL:
Expand All @@ -880,11 +870,6 @@ generateS390ImmOp(TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic memOp, TR::N
return cursor;
}
}
if (targetRegister != NULL && targetRegister->assignToHPR())
{
immOp = TR::InstOpCode::BAD;
ei_immOp = TR::InstOpCode::CIH;
}
else
{
if (cg->canUseGoldenEagleImmediateInstruction(value))
Expand Down Expand Up @@ -11999,8 +11984,6 @@ OMR::Z::TreeEvaluator::iRegLoadEvaluator(TR::Node * node, TR::CodeGenerator * cg
}

node->setRegister(globalReg);

globalReg->setAssignToHPR(false);
}

return globalReg;
Expand Down

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