Merge pull request #6227 from Akira1Saitoh/aarch64GCRPatching

AArch64: Implement Patchable GCRs
eclipse · Nov 5, 2021 · 2a36842 · 2a36842
2 parents f61b338 + 12820d2
commit 2a36842
Show file tree

Hide file tree

Showing 5 changed files with 64 additions and 3 deletions.
diff --git a/compiler/aarch64/codegen/ARM64BinaryEncoding.cpp b/compiler/aarch64/codegen/ARM64BinaryEncoding.cpp
@@ -29,6 +29,8 @@
 #include "codegen/InstructionDelegate.hpp"
 #include "codegen/Linkage.hpp"
 #include "codegen/Relocation.hpp"
+#include "compile/Compilation.hpp"
+#include "il/Node_inlines.hpp"
 #include "il/StaticSymbol.hpp"
 #include "runtime/CodeCacheManager.hpp"
 
@@ -452,12 +454,13 @@ uint8_t *TR::ARM64Trg1ImmSymInstruction::generateBinaryEncoding()
             cg()->addRelocation(new (cg()->trHeapMemory()) TR::LabelRelative24BitRelocation(cursor, label));
             }
          }
-      else if ((getOpCodeValue() == TR::InstOpCode::adr) && sym->isStartPC())
+      else if ((getOpCodeValue() == TR::InstOpCode::adr) && (sym->isStartPC() || sym->isGCRPatchPoint()))
          {
          intptr_t offset = reinterpret_cast<intptr_t>(reinterpret_cast<uint8_t *>(sym->getStaticSymbol()->getStaticAddress()) - cursor);
          if (!constantIsSignedImm21(offset))
             {
-            cg()->comp()->failCompilation<TR::CompilationException>("offset (%ld) is too far for adr", offset);
+            cg()->comp()->failCompilation<TR::CompilationException>("offset (%ld) is too far for adr (symbol = %s)", offset,
+                                                                     (sym->isStartPC() ? "<start-PC>" : "<gcr-patch-point>"));
             }
          setSourceImmediate(offset);
          }
@@ -536,6 +539,29 @@ uint8_t *TR::ARM64ZeroSrc1ImmInstruction::generateBinaryEncoding()
    insertSource1Register(toARM64Cursor(cursor));
    insertImmediateField(toARM64Cursor(cursor));
    insertNbit(toARM64Cursor(cursor));
+
+   TR::Compilation *comp = cg()->comp();
+   // If this memory reference is about my count for recompile,
+   // then it's the cmp instruction that I need to patch
+   if (comp->getOption(TR_EnableGCRPatching))
+      {
+      TR::Node *node = self()->getNode();
+      if (node && (node->getOpCodeValue() == TR::ificmpeq || node->getOpCodeValue() == TR::ificmpne))
+         {
+         if (node->getFirstChild()->getOpCodeValue() == TR::iload)
+            {
+            TR::SymbolReference *symref = node->getFirstChild()->getSymbolReference();
+            if (symref)
+               {
+               TR::Symbol *symbol = symref->getSymbol();
+               if (symbol && symbol->isCountForRecompile())
+                  {
+                  comp->getSymRefTab()->findOrCreateGCRPatchPointSymbolRef()->getSymbol()->getStaticSymbol()->setStaticAddress(cursor);
+                  }
+               }
+            }
+         }
+      }
    cursor += ARM64_INSTRUCTION_LENGTH;
    setBinaryLength(ARM64_INSTRUCTION_LENGTH);
    setBinaryEncoding(instructionStart);

diff --git a/compiler/aarch64/codegen/OMRMemoryReference.cpp b/compiler/aarch64/codegen/OMRMemoryReference.cpp
@@ -63,6 +63,12 @@ static void loadRelocatableConstant(TR::Node *node,
       return;
       }
 
+   if (symbol->isGCRPatchPoint())
+      {
+      generateTrg1ImmSymInstruction(cg, TR::InstOpCode::adr, node, reg, addr, symbol);
+      return;
+      }
+
    if (ref->isUnresolved() || comp->compileRelocatableCode())
       {
       TR::Node *GCRnode = node;

diff --git a/compiler/aarch64/codegen/OMRTreeEvaluator.cpp b/compiler/aarch64/codegen/OMRTreeEvaluator.cpp
@@ -2842,6 +2842,33 @@ OMR::ARM64::TreeEvaluator::lstoreEvaluator(TR::Node *node, TR::CodeGenerator *cg
 TR::Register *
 OMR::ARM64::TreeEvaluator::bstoreEvaluator(TR::Node *node, TR::CodeGenerator *cg)
    {
+   TR::Compilation *comp = cg->comp();
+   if (comp->getOption(TR_EnableGCRPatching))
+      {
+      TR::SymbolReference *symref = node->getSymbolReference();
+      if (symref)
+         {
+         TR::Symbol *symbol = symref->getSymbol();
+         if (symbol->isGCRPatchPoint())
+            {
+            TR::MemoryReference *tempMR = new (cg->trHeapMemory()) TR::MemoryReference(node, cg);
+            TR::SymbolReference *patchGCRHelperRef = cg->symRefTab()->findOrCreateRuntimeHelper(TR_ARM64PatchGCRHelper);
+            TR::RegisterDependencyConditions *deps = new (cg->trHeapMemory()) TR::RegisterDependencyConditions(0, 2, cg->trMemory());
+            TR::Register *tempReg = cg->allocateRegister();
+            deps->addPostCondition(tempMR->getBaseRegister(), TR::RealRegister::x0);
+            deps->addPostCondition(tempReg, TR::RealRegister::x1);
+            TR::Instruction *blInstruction = generateImmSymInstruction(cg, TR::InstOpCode::bl, node,
+                                                                        reinterpret_cast<uintptr_t>(patchGCRHelperRef->getMethodAddress()),
+                                                                        deps, patchGCRHelperRef, NULL);
+
+            cg->stopUsingRegister(tempReg);
+            cg->recursivelyDecReferenceCount(node->getFirstChild());
+            tempMR->decNodeReferenceCounts(cg);
+            cg->machine()->setLinkRegisterKilled(true);
+            return NULL;
+            }
+         }
+      }
    return commonStoreEvaluator(node, TR::InstOpCode::strbimm, cg);
    }
 

diff --git a/compiler/ras/Debug.cpp b/compiler/ras/Debug.cpp
@@ -4211,6 +4211,7 @@ TR_Debug::getRuntimeHelperName(int32_t index)
          case TR_ARM64backwardHalfWordArrayCopy:                   return "__bwHalfWordArrayCopy";
          case TR_ARM64interfaceCompleteSlot2:                      return "_interfaceCompleteSlot2";
          case TR_ARM64interfaceSlotsUnavailable:                   return "_interfaceSlotsUnavailable";
+         case TR_ARM64PatchGCRHelper:                              return "_patchGCRHelper" ;
          }
       }
 #endif

diff --git a/compiler/runtime/Helpers.inc b/compiler/runtime/Helpers.inc
@@ -515,7 +515,8 @@ SETVAL(TR_ARM64backwardWordArrayCopy,TR_FSRH+48)
 SETVAL(TR_ARM64backwardHalfWordArrayCopy,TR_FSRH+49)
 SETVAL(TR_ARM64interfaceCompleteSlot2,TR_FSRH+50)
 SETVAL(TR_ARM64interfaceSlotsUnavailable,TR_FSRH+51)
-SETVAL(TR_ARM64numRuntimeHelpers,TR_FSRH+52)
+SETVAL(TR_ARM64PatchGCRHelper,TR_FSRH+52)
+SETVAL(TR_ARM64numRuntimeHelpers,TR_FSRH+53)
 
 SETVAL(TR_S390longDivide,TR_FSRH)
 SETVAL(TR_S390interfaceCallHelper,TR_FSRH+1)