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Add CLWB to X86 support_features_test
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jmesyou committed Mar 6, 2024
1 parent 19993ce commit 2c3ffab
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Showing 3 changed files with 4 additions and 0 deletions.
1 change: 1 addition & 0 deletions compiler/env/ProcessorInfo.hpp
Original file line number Diff line number Diff line change
Expand Up @@ -188,6 +188,7 @@ inline uint32_t getFeatureFlags8Mask()
{
return TR_HLE
| TR_RTM
| TR_CLWB
| TR_AVX2
| TR_AVX512F
| TR_AVX512VL
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1 change: 1 addition & 0 deletions compiler/x/codegen/OMRCodeGenerator.hpp
Original file line number Diff line number Diff line change
Expand Up @@ -150,6 +150,7 @@ struct TR_X86ProcessorInfo
bool has36BitPageSizeExtension() {return testFeatureFlags(TR_36BitPageSizeExtension);}
bool hasProcessorSerialNumber() {return testFeatureFlags(TR_ProcessorSerialNumber);}
bool supportsCLFLUSHInstruction() {return testFeatureFlags(TR_CLFLUSHInstruction);}
bool supportsCLWBInstruction() {return testFeatureFlags8(TR_CLWB);}
bool supportsDebugTraceStore() {return testFeatureFlags(TR_DebugTraceStore);}
bool hasACPIRegisters() {return testFeatureFlags(TR_ACPIRegisters);}
bool supportsMMXInstructions() {return testFeatureFlags(TR_MMXInstructions);}
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2 changes: 2 additions & 0 deletions compiler/x/env/OMRCPU.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -349,6 +349,8 @@ OMR::X86::CPU::supports_feature_test(uint32_t feature)
return TR::CodeGenerator::getX86ProcessorInfo().hasProcessorSerialNumber() == ans;
case OMR_FEATURE_X86_CLFSH:
return TR::CodeGenerator::getX86ProcessorInfo().supportsCLFLUSHInstruction() == ans;
case OMR_FEATURE_X86_CLWB:
return TR::CodeGenerator::getX86ProcessorInfo().supportsCLWBInstruction() == ans;
case OMR_FEATURE_X86_DS:
return TR::CodeGenerator::getX86ProcessorInfo().supportsDebugTraceStore() == ans;
case OMR_FEATURE_X86_ACPI:
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