Use common fence instruction on ARM

eclipse · Jun 15, 2021 · 46b56b5 · 46b56b5
1 parent aba6226
commit 46b56b5
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Showing 6 changed files with 5 additions and 11 deletions.
diff --git a/compiler/arm/codegen/ARMBinaryEncoding.cpp b/compiler/arm/codegen/ARMBinaryEncoding.cpp
@@ -162,7 +162,7 @@ uint8_t *TR::ARMAdminInstruction::generateBinaryEncoding()
    uint8_t  *instructionStart = cg()->getBinaryBufferCursor();
    uint32_t i;
 
-   if (getOpCodeValue() == ARMOp_fence)
+   if (getOpCodeValue() == TR::InstOpCode::fence)
       {
       TR::Node  *fenceNode = getFenceNode();
       uint32_t  rtype     = fenceNode->getRelocationType();

diff --git a/compiler/arm/codegen/ARMDebug.cpp b/compiler/arm/codegen/ARMDebug.cpp
@@ -374,7 +374,7 @@ TR_Debug::print(TR::FILE *pOutFile, TR::ARMAdminInstruction * instr)
 
    printPrefix(pOutFile, instr);
    trfprintf(pOutFile, "%s\t", fullOpCodeName(instr));
-   if (instr->getOpCodeValue() == ARMOp_fence && instr->getFenceNode())
+   if (instr->getOpCodeValue() == TR::InstOpCode::fence && instr->getFenceNode())
       {
       TR::Node *fenceNode = instr->getFenceNode();
       if (fenceNode->getRelocationType() == TR_AbsoluteAddress)

diff --git a/compiler/arm/codegen/OMRInstOpCode.cpp b/compiler/arm/codegen/OMRInstOpCode.cpp
@@ -99,7 +99,6 @@ const OMR::ARM::InstOpCode::TR_OpCodeBinaryEntry OMR::ARM::InstOpCode::binaryEnc
    0x06BF0070,  // sxth
    0x06EF0070,  // uxtb
    0x06FF0070,  // uxth
-   0x00000000,  // fence
    0x00000000,  // ret
    0x00000000,  // wrtbar
    0x00000000,  // proc
@@ -394,9 +393,6 @@ ARMOpProp_Arch4,
 // uxth
 0,
 
-// fence
-0,
-
 // ret
 0,
 

diff --git a/compiler/arm/codegen/OMRInstOpCode.enum b/compiler/arm/codegen/OMRInstOpCode.enum
@@ -89,7 +89,6 @@
    ARMOp_sxth,             // Sign extend halfword
    ARMOp_uxtb,             // Zero extend byte
    ARMOp_uxth,             // Zero extend halfword
-   ARMOp_fence,            // Fence
    ARMOp_ret,              // Return
    ARMOp_wrtbar,           // Write barrier directive
    ARMOp_proc,             // Entry to the method

diff --git a/compiler/arm/codegen/OMRInstOpCode.enum.temp.defines b/compiler/arm/codegen/OMRInstOpCode.enum.temp.defines
@@ -87,7 +87,6 @@
 #define ARMOp_sxth OMR::InstOpCode::ARMOp_sxth
 #define ARMOp_uxtb OMR::InstOpCode::ARMOp_uxtb
 #define ARMOp_uxth OMR::InstOpCode::ARMOp_uxth
-#define ARMOp_fence OMR::InstOpCode::ARMOp_fence
 #define ARMOp_ret OMR::InstOpCode::ARMOp_ret
 #define ARMOp_wrtbar OMR::InstOpCode::ARMOp_wrtbar
 #define ARMOp_proc OMR::InstOpCode::ARMOp_proc

diff --git a/compiler/arm/codegen/OMRTreeEvaluator.cpp b/compiler/arm/codegen/OMRTreeEvaluator.cpp
@@ -3613,7 +3613,7 @@ TR::Register *OMR::ARM::TreeEvaluator::treetopEvaluator(TR::Node *node, TR::Code
 
 TR::Register *OMR::ARM::TreeEvaluator::exceptionRangeFenceEvaluator(TR::Node *node, TR::CodeGenerator *cg)
    {
-   generateAdminInstruction(cg, ARMOp_fence, node, node);
+   generateAdminInstruction(cg, TR::InstOpCode::fence, node, node);
    return NULL;
    }
 
@@ -3808,7 +3808,7 @@ TR::Register *OMR::ARM::TreeEvaluator::BBStartEvaluator(TR::Node *node, TR::Code
       }
 
    TR::Node * fenceNode = TR::Node::createRelative32BitFenceNode(node, &block->getInstructionBoundaries()._startPC);
-   TR::Instruction * fence = generateAdminInstruction(cg, ARMOp_fence, node, deps, fenceNode);
+   TR::Instruction * fence = generateAdminInstruction(cg, TR::InstOpCode::fence, node, deps, fenceNode);
 
    if (block->isCatchBlock())
       {
@@ -3846,7 +3846,7 @@ TR::Register *OMR::ARM::TreeEvaluator::BBEndEvaluator(TR::Node *node, TR::CodeGe
       }
 
    // put the dependencies (if any) on the fence
-   generateAdminInstruction(cg, ARMOp_fence, node, deps, fenceNode);
+   generateAdminInstruction(cg, TR::InstOpCode::fence, node, deps, fenceNode);
 
    return NULL;
    }