Use common dd instruction on ARM

eclipse · Jun 15, 2021 · aba6226 · aba6226
1 parent e4fe8b4
commit aba6226
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Showing 5 changed files with 10 additions and 16 deletions.
diff --git a/compiler/arm/codegen/FPTreeEvaluator.cpp b/compiler/arm/codegen/FPTreeEvaluator.cpp
@@ -1044,7 +1044,7 @@ TR::Register *OMR::ARM::TreeEvaluator::fconstEvaluator(TR::Node *node, TR::CodeG
    //cg->stopUsingRegister(tempReg);
 
    // Place the constant
-   generateImmInstruction(cg, ARMOp_dd, node, i32);
+   generateImmInstruction(cg, TR::InstOpCode::dd, node, i32);
    //armCG(cg)->findOrCreateFloatConstant(&value, TR::Float, cursor);
 
    if (noFPRA)
@@ -1107,13 +1107,13 @@ TR::Register *OMR::ARM::TreeEvaluator::dconstEvaluator(TR::Node *node, TR::CodeG
    //armCG(cg)->findOrCreateFloatConstant(&value, TR::Double, high, low);
    if (cg->comp()->target().cpu.isLittleEndian())
       {
-      generateImmInstruction(cg, ARMOp_dd, node, (int32_t)i64);
-      generateImmInstruction(cg, ARMOp_dd, node, (int32_t)((i64>>32) & 0xffffffff));
+      generateImmInstruction(cg, TR::InstOpCode::dd, node, (int32_t)i64);
+      generateImmInstruction(cg, TR::InstOpCode::dd, node, (int32_t)((i64>>32) & 0xffffffff));
       }
    else
       {
-      generateImmInstruction(cg, ARMOp_dd, node, (int32_t)((i64>>32) & 0xffffffff));
-      generateImmInstruction(cg, ARMOp_dd, node, (int32_t)i64);
+      generateImmInstruction(cg, TR::InstOpCode::dd, node, (int32_t)((i64>>32) & 0xffffffff));
+      generateImmInstruction(cg, TR::InstOpCode::dd, node, (int32_t)i64);
       }
 
    if (noFPRA)

diff --git a/compiler/arm/codegen/OMRCodeGenerator.cpp b/compiler/arm/codegen/OMRCodeGenerator.cpp
@@ -302,14 +302,14 @@ TR::Instruction *OMR::ARM::CodeGenerator::generateSwitchToInterpreterPrePrologue
    cursor = new (self()->trHeapMemory()) TR::ARMTrg1Src1Instruction(cursor, ARMOp_mov, node, gr4, lr, self());
    cursor = self()->getLinkage()->flushArguments(cursor);
    cursor = generateImmSymInstruction(self(), ARMOp_bl, node, (uintptr_t)revertToInterpreterSymRef->getMethodAddress(), new (self()->trHeapMemory()) TR::RegisterDependencyConditions((uint8_t)0,0, self()->trMemory()), revertToInterpreterSymRef, NULL, cursor);
-   cursor = generateImmInstruction(self(), ARMOp_dd, node, (int32_t)ramMethod, TR_RamMethod, cursor);
+   cursor = generateImmInstruction(self(), TR::InstOpCode::dd, node, (int32_t)ramMethod, TR_RamMethod, cursor);
 
    if (comp->getOption(TR_EnableHCR))
       comp->getStaticHCRPICSites()->push_front(cursor);
 
-   cursor = generateImmInstruction(self(), ARMOp_dd, node, (int32_t)helperAddr, TR_AbsoluteHelperAddress, helperSymRef, cursor);
+   cursor = generateImmInstruction(self(), TR::InstOpCode::dd, node, (int32_t)helperAddr, TR_AbsoluteHelperAddress, helperSymRef, cursor);
    // Used in FSD to store an  instruction
-   cursor = generateImmInstruction(self(), ARMOp_dd, node, 0, cursor);
+   cursor = generateImmInstruction(self(), TR::InstOpCode::dd, node, 0, cursor);
 
    return cursor;
    }
@@ -326,10 +326,10 @@ void OMR::ARM::CodeGenerator::beginInstructionSelection()
       if (methodSymbol->isJNI())
          {
          uintptr_t JNIMethodAddress = (uintptr_t) methodSymbol->getResolvedMethod()->startAddressForJNIMethod(comp);
-         cursor = new (self()->trHeapMemory()) TR::ARMImmInstruction(cursor, ARMOp_dd, startNode, (int32_t)JNIMethodAddress, self());
+         cursor = new (self()->trHeapMemory()) TR::ARMImmInstruction(cursor, TR::InstOpCode::dd, startNode, (int32_t)JNIMethodAddress, self());
          }
 
-      _returnTypeInfoInstruction = new (self()->trHeapMemory()) TR::ARMImmInstruction(cursor, ARMOp_dd, startNode, 0, self());
+      _returnTypeInfoInstruction = new (self()->trHeapMemory()) TR::ARMImmInstruction(cursor, TR::InstOpCode::dd, startNode, 0, self());
       new (self()->trHeapMemory()) TR::ARMAdminInstruction(_returnTypeInfoInstruction, ARMOp_proc, startNode, NULL, self());
 
       }

diff --git a/compiler/arm/codegen/OMRInstOpCode.cpp b/compiler/arm/codegen/OMRInstOpCode.cpp
@@ -103,7 +103,6 @@ const OMR::ARM::InstOpCode::TR_OpCodeBinaryEntry OMR::ARM::InstOpCode::binaryEnc
    0x00000000,  // ret
    0x00000000,  // wrtbar
    0x00000000,  // proc
-   0x00000000,  // dd
    0x0E070FBA,  // dmb_v6
    0xF57FF05F,  // dmb
    0xF57FF05E,  // dmb_st
@@ -407,9 +406,6 @@ ARMOpProp_Arch4,
 // proc
 0,
 
-// dd
-0,
-
 // dmb_v6
 0,
 

diff --git a/compiler/arm/codegen/OMRInstOpCode.enum b/compiler/arm/codegen/OMRInstOpCode.enum
@@ -93,7 +93,6 @@
    ARMOp_ret,              // Return
    ARMOp_wrtbar,           // Write barrier directive
    ARMOp_proc,             // Entry to the method
-   ARMOp_dd,               // define word
    ARMOp_dmb_v6,           // Data memory barrier
    ARMOp_dmb,              // Data memory barrier on ARMv7A
    ARMOp_dmb_st,           // Data write memory barrier on ARMv7A

diff --git a/compiler/arm/codegen/OMRInstOpCode.enum.temp.defines b/compiler/arm/codegen/OMRInstOpCode.enum.temp.defines
@@ -91,7 +91,6 @@
 #define ARMOp_ret OMR::InstOpCode::ARMOp_ret
 #define ARMOp_wrtbar OMR::InstOpCode::ARMOp_wrtbar
 #define ARMOp_proc OMR::InstOpCode::ARMOp_proc
-#define ARMOp_dd OMR::InstOpCode::ARMOp_dd
 #define ARMOp_dmb_v6 OMR::InstOpCode::ARMOp_dmb_v6
 #define ARMOp_dmb OMR::InstOpCode::ARMOp_dmb
 #define ARMOp_dmb_st OMR::InstOpCode::ARMOp_dmb_st