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Deprecate allocate64bitRegister and allocate64bitRegisterPair
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Now that we don't distinguish between `TR_GPR` and `TR_GPR64` the two
APIs map down to their non-64-bit counterparts and can thus be
removed.

Signed-off-by: Filip Jeremic <fjeremic@ca.ibm.com>
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@fjeremic
fjeremic committed Jan 21, 2019
1 parent bd81c7b commit 962af82
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Showing 12 changed files with 116 additions and 137 deletions.
11 changes: 0 additions & 11 deletions compiler/codegen/OMRCodeGenerator.cpp
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Expand Up @@ -1171,11 +1171,6 @@ TR::Register *OMR::CodeGenerator::allocateSinglePrecisionRegister(TR_RegisterKin
return temp;
}

TR::Register *OMR::CodeGenerator::allocate64bitRegister()
{
return self()->allocateRegister();
}

void OMR::CodeGenerator::apply8BitLabelRelativeRelocation(int32_t * cursor, TR::LabelSymbol * label)
{ *(int8_t *)cursor += (int8_t)(intptrj_t)label->getCodeLocation(); }
void OMR::CodeGenerator::apply12BitLabelRelativeRelocation(int32_t * cursor, TR::LabelSymbol * label, bool isCheckDisp)
Expand Down Expand Up @@ -3059,12 +3054,6 @@ void OMR::CodeGenerator::addAllocatedRegister(TR::Register * temp)
self()->startUsingRegister(temp);
}


TR::RegisterPair * OMR::CodeGenerator::allocate64bitRegisterPair(TR::Register * lo, TR::Register * ho)
{
return self()->allocateRegisterPair(lo, ho);
}

TR::RegisterPair * OMR::CodeGenerator::allocateRegisterPair(TR::Register * lo, TR::Register * ho)
{
TR::RegisterPair *temp = new (self()->trHeapMemory()) TR::RegisterPair(lo, ho);
Expand Down
2 changes: 0 additions & 2 deletions compiler/codegen/OMRCodeGenerator.hpp
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Expand Up @@ -1052,9 +1052,7 @@ class OMR_EXTENSIBLE CodeGenerator
TR::Register * allocateRegister(TR_RegisterKinds rk = TR_GPR);
TR::Register * allocateCollectedReferenceRegister();
TR::Register * allocateSinglePrecisionRegister(TR_RegisterKinds rk = TR_FPR);
TR::Register * allocate64bitRegister();

TR::RegisterPair * allocate64bitRegisterPair(TR::Register * lo = 0, TR::Register * ho = 0);
TR::RegisterPair * allocateRegisterPair(TR::Register * lo = 0, TR::Register * ho = 0);
TR::RegisterPair * allocateSinglePrecisionRegisterPair(TR::Register * lo = 0, TR::Register * ho = 0);
TR::RegisterPair * allocateFloatingPointRegisterPair(TR::Register * lo = 0, TR::Register * ho = 0);
Expand Down
2 changes: 1 addition & 1 deletion compiler/z/codegen/BinaryAnalyser.cpp
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Expand Up @@ -371,7 +371,7 @@ TR_S390BinaryAnalyser::longSubtractAnalyser(TR::Node * root)
{
if (getCopyReg1())
{
TR::Register * thirdReg = cg()->allocate64bitRegister();
TR::Register * thirdReg = cg()->allocateRegister();

root->setRegister(thirdReg);
generateRRInstruction(cg(), TR::InstOpCode::LGR, root, thirdReg, firstRegister);
Expand Down
2 changes: 1 addition & 1 deletion compiler/z/codegen/BinaryCommutativeAnalyser.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -365,7 +365,7 @@ TR_S390BinaryCommutativeAnalyser::genericAnalyser(TR::Node * root, TR::InstOpCod
if(z14OpCode != TR::InstOpCode::BAD)
{
bool isCanClobberFirstReg = cg()->canClobberNodesRegister(firstChild);
nodeReg = isCanClobberFirstReg ? firstRegister : cg()->allocate64bitRegister();
nodeReg = isCanClobberFirstReg ? firstRegister : cg()->allocateRegister();
generateRRFInstruction(cg(), z14OpCode, root, nodeReg, firstRegister, secondRegister, 0, 0);
}
}
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34 changes: 17 additions & 17 deletions compiler/z/codegen/BinaryEvaluator.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1108,7 +1108,7 @@ lDivRemGenericEvaluator64(TR::Node * node, TR::CodeGenerator * cg, bool isDivisi
if (firstChild == secondChild)
{
TR::Register * sourceRegister = cg->evaluate(firstChild);
TR::Register * returnRegister = cg->allocate64bitRegister();
TR::Register * returnRegister = cg->allocateRegister();
int32_t retValue = 0; // default REM

if (isDivision)
Expand Down Expand Up @@ -1238,8 +1238,8 @@ lDivRemGenericEvaluator64(TR::Node * node, TR::CodeGenerator * cg, bool isDivisi
TR::RegisterDependencyConditions *deps = NULL;
if (!firstChild->isNonNegative())
{
TR::Register * tempRegister1 = cg->allocate64bitRegister();
TR::Register * tempRegister2 = cg->allocate64bitRegister();
TR::Register * tempRegister1 = cg->allocateRegister();
TR::Register * tempRegister2 = cg->allocateRegister();
generateRSInstruction(cg, TR::InstOpCode::SRAG, node, tempRegister2, firstRegister, 63);
generateRRInstruction(cg, TR::InstOpCode::LGR, node, tempRegister1, firstRegister);
generateRILInstruction(cg, TR::InstOpCode::NIHF, node, tempRegister2, static_cast<int32_t>((absValueOfDenominator-1)>>32) );
Expand Down Expand Up @@ -1287,11 +1287,11 @@ lDivRemGenericEvaluator64(TR::Node * node, TR::CodeGenerator * cg, bool isDivisi
{
numPostConditions++; // for sourceRegister (the divisor)
remRegister = cg->gprClobberEvaluate(firstChild);
quoRegister = cg->allocate64bitRegister();
quoRegister = cg->allocateRegister();
}
else
{
remRegister = cg->allocate64bitRegister();
remRegister = cg->allocateRegister();
quoRegister = cg->gprClobberEvaluate(firstChild);
}

Expand Down Expand Up @@ -1346,7 +1346,7 @@ lDivRemGenericEvaluator64(TR::Node * node, TR::CodeGenerator * cg, bool isDivisi
else
{
absDividendRegIsTemp = true;
absDividendReg = cg->allocate64bitRegister();
absDividendReg = cg->allocateRegister();
// LGPR is needed so negative numbers do not always take the slow path after the logical compare (but functionally it is not needed)
generateRRInstruction(cg, TR::InstOpCode::LPGR, node, absDividendReg, remRegister);
}
Expand Down Expand Up @@ -1629,7 +1629,7 @@ genericLongShiftSingle(TR::Node * node, TR::CodeGenerator * cg, TR::InstOpCode::
TR::Node * secondChild = node->getSecondChild();
TR::Node * firstChild = node->getFirstChild();
TR::Register * srcReg = NULL;
TR::Register * trgReg = cg->allocate64bitRegister();
TR::Register * trgReg = cg->allocateRegister();
TR::Register * src2Reg = NULL;
TR::MemoryReference * tempMR = NULL;

Expand Down Expand Up @@ -2121,7 +2121,7 @@ genericRotateLeft(TR::Node * node, TR::CodeGenerator * cg)
TR::Node* otherData = andChild->getFirstChild();
TR::Register* toReg = cg->evaluate(otherData);
TR::Register* fromReg = cg->evaluate(data);
TR::Register* targetReg = cg->allocate64bitRegister();
TR::Register* targetReg = cg->allocateRegister();

generateRRInstruction(cg, TR::InstOpCode::LGR, node, targetReg, toReg);
generateRIEInstruction(cg, TR::InstOpCode::RISBG, node, targetReg, fromReg, bitPos, bitPos, shiftBy);
Expand All @@ -2141,7 +2141,7 @@ genericRotateLeft(TR::Node * node, TR::CodeGenerator * cg)
{
TR::Register* toReg = cg->evaluate(andChild->getFirstChild());
TR::Register* fromReg = cg->evaluate(shiftChild->getFirstChild());
TR::Register* targetReg = cg->allocate64bitRegister();
TR::Register* targetReg = cg->allocateRegister();
generateRRInstruction(cg, TR::InstOpCode::LGR, node, targetReg, toReg);
generateRIEInstruction(cg, TR::InstOpCode::RISBG, node, targetReg, fromReg, 0, bitPos, shiftBy);
cg->decReferenceCount(andChild->getFirstChild());
Expand Down Expand Up @@ -2187,7 +2187,7 @@ genericRotateLeft(TR::Node * node, TR::CodeGenerator * cg)
lastBit = 63 - shiftBy;
TR::Register* toReg = cg->evaluate(otherChild);
TR::Register* fromReg = cg->evaluate(shiftChild->getFirstChild());
TR::Register* targetReg = cg->allocate64bitRegister();
TR::Register* targetReg = cg->allocateRegister();
TR::InstOpCode::Mnemonic opcode = TR::InstOpCode::ROSBG;
if (node->getOpCodeValue() == TR::lxor)
opcode = TR::InstOpCode::RXSBG;
Expand Down Expand Up @@ -2977,7 +2977,7 @@ OMR::Z::TreeEvaluator::dualMulHelper64(TR::Node * node, TR::Node * lmulNode, TR:
TR::Register * secondRegister = cg->evaluate(secondChild);
TR::Instruction * cursor = NULL;
TR::Register * lmulTargetRegister = cg->gprClobberEvaluate(firstChild);
TR::Register * lumulhTargetRegister = cg->allocate64bitRegister();
TR::Register * lumulhTargetRegister = cg->allocateRegister();
TR::RegisterPair * trgtRegPair = cg->allocateConsecutiveRegisterPair(lmulTargetRegister, lumulhTargetRegister);

TR::RegisterDependencyConditions * dependencies = new (cg->trHeapMemory()) TR::RegisterDependencyConditions(0, 3, cg);
Expand Down Expand Up @@ -3383,7 +3383,7 @@ lmulHelper64(TR::Node * node, TR::CodeGenerator * cg)

sourceRegister = cg->evaluate(firstChild);
bool canClobber = cg->canClobberNodesRegister(firstChild);
targetRegister = !canClobber ? cg->allocate64bitRegister() : sourceRegister;
targetRegister = !canClobber ? cg->allocateRegister() : sourceRegister;

if (create_LA)
{
Expand Down Expand Up @@ -3537,7 +3537,7 @@ OMR::Z::TreeEvaluator::lmulhEvaluator(TR::Node * node, TR::CodeGenerator * cg)
TR::Node * firstChild = node->getFirstChild();
TR::Node * secondChild = node->getSecondChild();
TR::Register * firstRegister = cg->gprClobberEvaluate(firstChild);
TR::Register * targetRegister = cg->allocate64bitRegister();
TR::Register * targetRegister = cg->allocateRegister();
TR::Register * sourceRegister;
TR::Register * resultRegister;
TR::Compilation *comp = cg->comp();
Expand Down Expand Up @@ -4297,7 +4297,7 @@ OMR::Z::TreeEvaluator::lnegEvaluator(TR::Node * node, TR::CodeGenerator * cg)
if (TR::Compiler->target.is64Bit() || cg->use64BitRegsOn32Bit())
{
TR::Register * sourceRegister;
targetRegister = cg->allocate64bitRegister();
targetRegister = cg->allocateRegister();

if (firstChild->getOpCodeValue() == TR::labs && firstChild->getReferenceCount() == 1 && firstChild->getRegister() == NULL)
{
Expand Down Expand Up @@ -4598,15 +4598,15 @@ OMR::Z::TreeEvaluator::integerRolEvaluator(TR::Node *node, TR::CodeGenerator *cg
else
{
sourceRegister = cg->evaluate(firstChild);
targetRegister = nodeIs64Bit ? cg->allocate64bitRegister() : cg->allocateRegister();
targetRegister = nodeIs64Bit ? cg->allocateRegister() : cg->allocateRegister();
generateRSInstruction(cg, nodeIs64Bit ? TR::InstOpCode::RLLG : TR::InstOpCode::RLL, node, targetRegister, sourceRegister, rotateAmount);
}
}
else if(useRegPairs)
{
sourceRegister = cg->evaluate(firstChild);
targetRegister = cg->allocateConsecutiveRegisterPair();
TR::Register * scratchReg = cg->allocate64bitRegister();
TR::Register * scratchReg = cg->allocateRegister();

// Shift high order by 32 bit and loaded into temp scratch register
generateRSInstruction(cg, TR::InstOpCode::SLLG, node, scratchReg, sourceRegister->getHighOrder(), 32);
Expand All @@ -4632,7 +4632,7 @@ OMR::Z::TreeEvaluator::integerRolEvaluator(TR::Node *node, TR::CodeGenerator *cg
else
{
sourceRegister = cg->evaluate(firstChild);
targetRegister = nodeIs64Bit ? cg->allocate64bitRegister() : cg->allocateRegister();
targetRegister = nodeIs64Bit ? cg->allocateRegister() : cg->allocateRegister();

TR::MemoryReference* memRef = generateS390MemoryReference(cg);
memRef->populateMemoryReference(secondChild, cg);
Expand Down
6 changes: 3 additions & 3 deletions compiler/z/codegen/ControlFlowEvaluator.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -627,7 +627,7 @@ generateS390lcmpEvaluator64(TR::Node * node, TR::CodeGenerator * cg, TR::InstOpC
TR_ASSERT(isBoolean, "Coparison node %p is not boolean\n",node);

if (cg->use64BitRegsOn32Bit())
targetRegister = cg->allocate64bitRegister();
targetRegister = cg->allocateRegister();
else
targetRegister = cg->allocateRegister();

Expand Down Expand Up @@ -1006,7 +1006,7 @@ lcmpHelper64(TR::Node * node, TR::CodeGenerator * cg)
TR::LabelSymbol * labelGT = generateLabelSymbol(cg);
TR::LabelSymbol * labelLT = generateLabelSymbol(cg);

TR::Register * targetRegister = cg->allocate64bitRegister();
TR::Register * targetRegister = cg->allocateRegister();

TR::Node * firstChild = node->getFirstChild();
TR::Node * secondChild = node->getSecondChild();
Expand Down Expand Up @@ -1225,7 +1225,7 @@ OMR::Z::TreeEvaluator::returnEvaluator(TR::Node * node, TR::CodeGenerator * cg)

if (cg->use64BitRegsOn32Bit())
{
TR::Register * highRegister = cg->allocate64bitRegister();
TR::Register * highRegister = cg->allocateRegister();

generateRSInstruction(cg, TR::InstOpCode::SRLG, node, highRegister, returnValRegister, 32);

Expand Down
8 changes: 4 additions & 4 deletions compiler/z/codegen/FPTreeEvaluator.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -655,7 +655,7 @@ commonLong2FloatEvaluator(TR::Node * node, TR::CodeGenerator * cg)
TR::RegisterDependencyConditions *deps = depsNeeded > 0 ? new (cg->trHeapMemory()) TR::RegisterDependencyConditions(0, depsNeeded, cg) : NULL;
TR::Node *srcNode = node->getFirstChild();
TR::Register *srcReg = cg->evaluate(srcNode);
TR::Register *gprTemp64 = cg->allocate64bitRegister();
TR::Register *gprTemp64 = cg->allocateRegister();

// the 64 bit register gprTemp64 is going to be clobbered and R0 is safe to clobber (so are R1,R15)
if (restrictToGPR0)
Expand Down Expand Up @@ -1283,7 +1283,7 @@ OMR::Z::TreeEvaluator::ibits2fEvaluator(TR::Node * node, TR::CodeGenerator * cg)
if (TR::Compiler->target.cpu.getS390SupportsFPE() && !disabled)
{
TR::Register *tempreg;
tempreg = cg->allocate64bitRegister();
tempreg = cg->allocateRegister();
generateRSInstruction(cg, TR::InstOpCode::SLLG, node, tempreg, sourceReg, 32);
generateRRInstruction(cg, TR::InstOpCode::LDGR, node, targetReg, tempreg);
cg->stopUsingRegister(tempreg);
Expand Down Expand Up @@ -1723,7 +1723,7 @@ f2lHelper64(TR::Node * node, TR::CodeGenerator * cg)
TR_ASSERT( TR::Compiler->target.is64Bit() || cg->use64BitRegsOn32Bit(), "f2lHelper64() is for 64bit code-gen only!");
TR::Node * firstChild = node->getFirstChild();
TR::Register * floatRegister = cg->evaluate(firstChild);
TR::Register * targetRegister = cg->allocate64bitRegister();
TR::Register * targetRegister = cg->allocateRegister();

TR::LabelSymbol * cFlowRegionStart = generateLabelSymbol(cg);
TR::LabelSymbol * cFlowRegionEnd = generateLabelSymbol(cg);
Expand Down Expand Up @@ -1941,7 +1941,7 @@ d2lHelper64(TR::Node * node, TR::CodeGenerator * cg)

TR::Node * firstChild = node->getFirstChild();
TR::Register * floatRegister = cg->evaluate(firstChild);
TR::Register * targetRegister = cg->allocate64bitRegister();
TR::Register * targetRegister = cg->allocateRegister();

TR::LabelSymbol * cFlowRegionStart = NULL;
TR::LabelSymbol * label1 = NULL;
Expand Down
2 changes: 1 addition & 1 deletion compiler/z/codegen/OMRCodeGenerator.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3848,7 +3848,7 @@ OMR::Z::CodeGenerator::allocateClobberableRegister(TR::Register *srcRegister)
}
else //todo: what about FPR?
{
targetRegister = self()->allocate64bitRegister();
targetRegister = self()->allocateRegister();
}

if (srcRegister->containsInternalPointer())
Expand Down
10 changes: 1 addition & 9 deletions compiler/z/codegen/OMRLinkage.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2466,16 +2466,8 @@ OMR::Z::Linkage::buildArgs(TR::Node * callNode, TR::RegisterDependencyConditions
{
//In this case, private and system linkage use same regs for return value
TR::Register * resultRegLow = self()->cg()->allocateRegister();
TR::Register * resultRegHigh = NULL;
TR::Register * resultRegHigh = self()->cg()->allocateRegister();

if (self()->cg()->use64BitRegsOn32Bit())
{
resultRegHigh = self()->cg()->allocate64bitRegister();
}
else
{
resultRegHigh = self()->cg()->allocateRegister();
}
self()->cg()->setRealRegisterAssociation(resultRegLow, self()->getLongLowReturnRegister());
dependencies->addPostCondition(resultRegLow, self()->getLongLowReturnRegister(),DefinesDependentRegister);
killMask &= (~(0x1L << REGINDEX(self()->getLongLowReturnRegister())));
Expand Down
16 changes: 8 additions & 8 deletions compiler/z/codegen/OMRMemoryReference.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -611,7 +611,7 @@ OMR::Z::MemoryReference::MemoryReference(TR::Node * rootLoadOrStore, TR::CodeGen
// Storing to the symbol reference
TR::Register * tempReg;
if (TR::Compiler->target.is64Bit())
tempReg = cg->allocate64bitRegister();
tempReg = cg->allocateRegister();
else
tempReg = cg->allocateRegister();
self()->setBaseRegister(tempReg, cg);
Expand Down Expand Up @@ -873,7 +873,7 @@ OMR::Z::MemoryReference::MemoryReference(TR::Snippet * s, TR::CodeGenerator * cg
if (cg->isLiteralPoolOnDemandOn())
{
if (TR::Compiler->target.is64Bit())
self()->setBaseRegister(cg->allocate64bitRegister(), cg);
self()->setBaseRegister(cg->allocateRegister(), cg);
else
self()->setBaseRegister(cg->allocateRegister(), cg);
generateLoadLiteralPoolAddress(cg, node, _baseRegister);
Expand Down Expand Up @@ -1917,7 +1917,7 @@ OMR::Z::MemoryReference::consolidateRegisters(TR::Node * node, TR::CodeGenerator
if (node && node->isInternalPointer() && node->getPinningArrayPointer())
{
if (TR::Compiler->target.is64Bit())
tempTargetRegister = cg->allocate64bitRegister();
tempTargetRegister = cg->allocateRegister();
else
tempTargetRegister = cg->allocateRegister();

Expand All @@ -1932,7 +1932,7 @@ OMR::Z::MemoryReference::consolidateRegisters(TR::Node * node, TR::CodeGenerator
else
{
if (TR::Compiler->target.is64Bit())
tempTargetRegister = cg->allocate64bitRegister();
tempTargetRegister = cg->allocateRegister();
else
tempTargetRegister = cg->allocateRegister();
}
Expand Down Expand Up @@ -2097,7 +2097,7 @@ OMR::Z::MemoryReference::enforce4KDisplacementLimit(TR::Node * node, TR::CodeGen
{
TR::Register * tempTargetRegister = NULL;
if (TR::Compiler->target.is64Bit())
tempTargetRegister = cg->allocate64bitRegister();
tempTargetRegister = cg->allocateRegister();
else
tempTargetRegister = cg->allocateRegister();
TR::MemoryReference * interimMemoryReference = generateS390MemoryReference(cg);
Expand Down Expand Up @@ -2167,7 +2167,7 @@ OMR::Z::MemoryReference::enforceDisplacementLimit(TR::Node * node, TR::CodeGener
TR_ASSERT( node,"node should be non-null for enforceDisplacementLimit\n");
TR::Register * tempTargetRegister;
if (TR::Compiler->target.is64Bit())
tempTargetRegister = cg->allocate64bitRegister();
tempTargetRegister = cg->allocateRegister();
else
tempTargetRegister = cg->allocateRegister();

Expand Down Expand Up @@ -2220,7 +2220,7 @@ OMR::Z::MemoryReference::eliminateNegativeDisplacement(TR::Node * node, TR::Code

TR::Register * tempTargetRegister;
if (TR::Compiler->target.is64Bit())
tempTargetRegister = cg->allocate64bitRegister();
tempTargetRegister = cg->allocateRegister();
else
tempTargetRegister = cg->allocateRegister();
TR::MemoryReference * interimMemoryReference = generateS390MemoryReference(cg);
Expand Down Expand Up @@ -2269,7 +2269,7 @@ OMR::Z::MemoryReference::separateIndexRegister(TR::Node * node, TR::CodeGenerato
}
TR::Register * tempTargetRegister = NULL;
if (TR::Compiler->target.is64Bit())
tempTargetRegister = cg->allocate64bitRegister();
tempTargetRegister = cg->allocateRegister();
else
tempTargetRegister = cg->allocateRegister();
TR::MemoryReference * interimMemoryReference = generateS390MemoryReference(cg);
Expand Down
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