AArch64: Int32 Support for Vector Multiplication

This commit accommodates Int32 support for vector multiplication operations. Signed-off-by: Md. Alvee Noor <mnoor@unb.ca>
eclipse · Jun 16, 2021 · 9b9f82d · 9b9f82d
1 parent ea6ff48
commit 9b9f82d
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diff --git a/compiler/aarch64/codegen/ARM64Debug.cpp b/compiler/aarch64/codegen/ARM64Debug.cpp
@@ -743,6 +743,7 @@ static const char *opCodeToNameMap[] =
    "vfsub2d",
    "vmul16b",
    "vmul8h",
+   "vmul4s",
    "vfmul4s",
    "vfmul2d",
    "vfdiv4s",

diff --git a/compiler/aarch64/codegen/BinaryEvaluator.cpp b/compiler/aarch64/codegen/BinaryEvaluator.cpp
@@ -351,6 +351,9 @@ OMR::ARM64::TreeEvaluator::vmulEvaluator(TR::Node *node, TR::CodeGenerator *cg)
       case TR::VectorInt16:
          mulOp = TR::InstOpCode::vmul8h;
          break;
+      case TR::VectorInt32:
+         mulOp = TR::InstOpCode::vmul4s;
+         break;
       case TR::VectorFloat:
          mulOp = TR::InstOpCode::vfmul4s;
          break;

diff --git a/compiler/aarch64/codegen/OMRInstOpCode.enum b/compiler/aarch64/codegen/OMRInstOpCode.enum
@@ -721,6 +721,7 @@
 		vfsub2d,                                                  	/* 0x4EE0D400	FSUB      	 */
 		vmul16b,                                                  	/* 0x4E209C00	MUL      	 */
 		vmul8h,                                                  	/* 0x4E609C00	MUL      	 */
+		vmul4s,                                                  	/* 0x4EA09C00	MUL      	 */
 		vfmul4s,                                                  	/* 0x6E20DC00	FMUL      	 */
 		vfmul2d,                                                  	/* 0x6E60DC00	FMUL      	 */
 		vfdiv4s,                                                  	/* 0x6E20FC00	FDIV      	 */

diff --git a/compiler/aarch64/codegen/OpBinary.cpp b/compiler/aarch64/codegen/OpBinary.cpp
@@ -727,6 +727,7 @@ const OMR::ARM64::InstOpCode::OpCodeBinaryEntry OMR::ARM64::InstOpCode::binaryEn
 		0x4EE0D400,	/* FSUB      	vfsub2d	 */
 		0x4E209C00,	/* MUL      	vmul16b	 */
 		0x4E609C00,	/* MUL      	vmul8h	 */
+		0x4EA09C00,	/* MUL      	vmul4s	 */
 		0x6E20DC00,	/* FMUL      	vfmul4s	 */
 		0x6E60DC00,	/* FMUL      	vfmul2d	 */
 		0x6E20FC00,	/* FDIV      	vfdiv4s	 */