Migrate retn to the common codegen

We also rename `ret` to `retn` to avoid name clashing on backends which define `ret` to be an actual instruction.
eclipse · May 13, 2021 · c1b3520 · c1b3520
1 parent 9c45612
commit c1b3520
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Showing 18 changed files with 43 additions and 43 deletions.
diff --git a/compiler/aarch64/codegen/ARM64Debug.cpp b/compiler/aarch64/codegen/ARM64Debug.cpp
@@ -99,6 +99,8 @@ static const char *opCodeToNameMap[] =
    "fence",
    "label",
    "proc",
+   "retn",
+   "vgnop",
    "cbzw",
    "cbnzw",
    "cbzx",

diff --git a/compiler/aarch64/codegen/OMRInstOpCode.enum b/compiler/aarch64/codegen/OMRInstOpCode.enum
@@ -733,7 +733,6 @@
 /* Hint instructions */
 		nop,                                                    	/* 0xD503201F   NOP          */
 /* Internal OpCodes */
-		retn,  // Return
 		vgdnop, // Virtual Guard NOP instruction
 		ARM64LastOp = vgdnop,
 		ARM64NumOpCodes = ARM64LastOp+1,
diff --git a/compiler/codegen/OMRInstOpCode.enum b/compiler/codegen/OMRInstOpCode.enum
@@ -29,4 +29,6 @@
    dd,                 // Define Doubleword
    fence,              // Fence
    label,              // Destination of a jump
-   proc,               // Entry to the method
+   proc,               // Entry to the method
+   retn,               // Return
+   vgnop,              // Virtual Guard NOP
diff --git a/compiler/p/codegen/ControlFlowEvaluator.cpp b/compiler/p/codegen/ControlFlowEvaluator.cpp
@@ -1594,7 +1594,7 @@ TR::Register *OMR::Power::TreeEvaluator::ireturnEvaluator(TR::Node *node, TR::Co
                 linkageProperties.getIntegerReturnRegister();
    TR::RegisterDependencyConditions *dependencies = new (cg->trHeapMemory()) TR::RegisterDependencyConditions(1, 0, cg->trMemory());
    dependencies->addPreCondition(returnRegister, machineReturnRegister);
-   generateAdminInstruction(cg, TR::InstOpCode::ret, node);
+   generateAdminInstruction(cg, TR::InstOpCode::retn, node);
    generateDepInstruction(cg, TR::InstOpCode::blr, node, dependencies);
    cg->decReferenceCount(node->getFirstChild());
    return NULL;
@@ -1626,7 +1626,7 @@ TR::Register *OMR::Power::TreeEvaluator::lreturnEvaluator(TR::Node *node, TR::Co
       dependencies->addPreCondition(lowReg, machineLowReturnRegister);
       dependencies->addPreCondition(highReg, machineHighReturnRegister);
       }
-   generateAdminInstruction(cg, TR::InstOpCode::ret, node);
+   generateAdminInstruction(cg, TR::InstOpCode::retn, node);
    generateDepInstruction(cg, TR::InstOpCode::blr, node, dependencies);
    cg->decReferenceCount(node->getFirstChild());
    return NULL;
@@ -1636,7 +1636,7 @@ TR::Register *OMR::Power::TreeEvaluator::lreturnEvaluator(TR::Node *node, TR::Co
 
 TR::Register *OMR::Power::TreeEvaluator::returnEvaluator(TR::Node *node, TR::CodeGenerator *cg)
    {
-   generateAdminInstruction(cg, TR::InstOpCode::ret, node);
+   generateAdminInstruction(cg, TR::InstOpCode::retn, node);
    generateInstruction(cg, TR::InstOpCode::blr, node);
    return NULL;
    }

diff --git a/compiler/p/codegen/FPTreeEvaluator.cpp b/compiler/p/codegen/FPTreeEvaluator.cpp
@@ -663,7 +663,7 @@ TR::Register *OMR::Power::TreeEvaluator::freturnEvaluator(TR::Node *node, TR::Co
                 linkageProperties.getFloatReturnRegister();
    TR::RegisterDependencyConditions *dependencies = new (cg->trHeapMemory()) TR::RegisterDependencyConditions(1, 0, cg->trMemory());
    dependencies->addPreCondition(returnRegister, machineReturnRegister);
-   generateAdminInstruction(cg, TR::InstOpCode::ret, node);
+   generateAdminInstruction(cg, TR::InstOpCode::retn, node);
    generateDepInstruction(cg, TR::InstOpCode::blr, node, dependencies);
    cg->decReferenceCount(node->getFirstChild());
    return NULL;

diff --git a/compiler/p/codegen/OMRInstOpCode.enum b/compiler/p/codegen/OMRInstOpCode.enum
@@ -539,7 +539,6 @@
    nop,              // NoOp (ori)
    genop,            // Group Ending NoOp (ori)
    shdfence,         // Scheduling Fence
-   ret,              // Return
 // rxor,             // Rotate & XOR
    wrtbar,           // Write barrier directive
    vgdnop,           // Virtual Guard NOP instruction

diff --git a/compiler/p/codegen/OMRInstOpCode.hpp b/compiler/p/codegen/OMRInstOpCode.hpp
@@ -155,7 +155,7 @@ class InstOpCode: public OMR::InstOpCode
                            _mnemonic==mulhwu ||
                            _mnemonic==mulhdu;}
 
-   bool isAdmin() {return _mnemonic==ret      ||
+   bool isAdmin() {return _mnemonic==retn     ||
                           _mnemonic==fence    ||
                           _mnemonic==proc     ||
                           _mnemonic==assocreg ||

diff --git a/compiler/p/codegen/OMRInstOpCodeProperties.hpp b/compiler/p/codegen/OMRInstOpCodeProperties.hpp
@@ -91,6 +91,17 @@
    /* .properties  = */ PPCOpProp_None,
    },
 
+   {
+   /* .mnemonic    = */ OMR::InstOpCode::retn,
+   /* .name        = */ "retn",
+   /* .description =    "Return", */
+   /* .prefix      = */ 0x00000000,
+   /* .opcode      = */ 0x00000000,
+   /* .format      = */ FORMAT_NONE,
+   /* .minimumALS  = */ OMR_PROCESSOR_PPC_UNKNOWN,
+   /* .properties  = */ PPCOpProp_None,
+   },
+
    {
    /* .mnemonic    = */ OMR::InstOpCode::add,
    /* .name        = */ "add",
@@ -6246,17 +6257,6 @@
    /* .properties  = */ PPCOpProp_SyncSideEffectFree,
    },
 
-   {
-   /* .mnemonic    = */ OMR::InstOpCode::ret,
-   /* .name        = */ "ret",
-   /* .description =    "Return", */
-   /* .prefix      = */ 0x00000000,
-   /* .opcode      = */ 0x00000000,
-   /* .format      = */ FORMAT_NONE,
-   /* .minimumALS  = */ OMR_PROCESSOR_PPC_UNKNOWN,
-   /* .properties  = */ PPCOpProp_None,
-   },
-
    /* { */
    /* .mnemonic    =    OMR::InstOpCode::rxor, */
    /* .name        =    "rxor", */

diff --git a/compiler/p/codegen/PPCBinaryEncoding.cpp b/compiler/p/codegen/PPCBinaryEncoding.cpp
@@ -1299,7 +1299,7 @@ int32_t TR::PPCConditionalBranchInstruction::estimateBinaryLength(int32_t curren
 
 TR::Instruction *TR::PPCAdminInstruction::expandInstruction()
    {
-   if (getOpCodeValue() == TR::InstOpCode::ret)
+   if (getOpCodeValue() == TR::InstOpCode::retn)
       {
       cg()->getLinkage()->createEpilogue(self());
       }

diff --git a/compiler/riscv/codegen/OMRInstOpCode.enum b/compiler/riscv/codegen/OMRInstOpCode.enum
@@ -33,6 +33,4 @@
 #include <riscv-opc.h>
 #undef DECLARE_INSN
 /* Internal OpCodes */
-		retn,  // Return
-		RVLastOp = retn,
-		RVNumOpCodes = RVLastOp+1,
+		RVNumOpCodes,
diff --git a/compiler/riscv/codegen/RVDebug.cpp b/compiler/riscv/codegen/RVDebug.cpp
@@ -45,13 +45,14 @@ static const char *opCodeToNameMap[] =
    "fence",
    "label",
    "proc",
+   "retn",
+   "vgnop",
 /*
  * RISC-V instructions
  */
 #define DECLARE_INSN(mnemonic, match, mask) #mnemonic,
 #include <riscv-opc.h>
 #undef DECLARE_INSN
-   "return",
    };
 
 const char *

diff --git a/compiler/z/codegen/ControlFlowEvaluator.cpp b/compiler/z/codegen/ControlFlowEvaluator.cpp
@@ -734,7 +734,7 @@ OMR::Z::TreeEvaluator::returnEvaluator(TR::Node * node, TR::CodeGenerator * cg)
          break;
       }
 
-   TR::Instruction * inst = generateS390PseudoInstruction(cg, TR::InstOpCode::RET, node, dependencies);
+   TR::Instruction * inst = generateS390PseudoInstruction(cg, TR::InstOpCode::retn, node, dependencies);
    if (cg->supportsBranchPreload())
       {
       int32_t frequency = comp->getCurrentBlock()->getFrequency();

diff --git a/compiler/z/codegen/InstOpCode.cpp b/compiler/z/codegen/InstOpCode.cpp
@@ -59,7 +59,7 @@ OMR::Z::InstOpCode::hasBypass()
 uint32_t
 OMR::Z::InstOpCode::isAdmin()
    {
-   return (_mnemonic == RET ||
+   return (_mnemonic == retn ||
            _mnemonic == assocreg ||
            _mnemonic == DEPEND ||
            _mnemonic == fence ||

diff --git a/compiler/z/codegen/OMRCodeGenerator.cpp b/compiler/z/codegen/OMRCodeGenerator.cpp
@@ -2000,7 +2000,7 @@ OMR::Z::CodeGenerator::doBinaryEncoding()
          self()->setCurrentBlock(data.cursorInstruction->getNode()->getBlock());
          }
 
-      if (data.cursorInstruction->getOpCodeValue() == TR::InstOpCode::RET)
+      if (data.cursorInstruction->getOpCodeValue() == TR::InstOpCode::retn)
          {
 
          if (skipOneReturn == false)
@@ -2010,8 +2010,8 @@ OMR::Z::CodeGenerator::doBinaryEncoding()
             data.cursorInstruction = temp->getNext();
 
             /* skipOneReturn only if epilog is generated which is indicated by instructions being */
-            /* inserted before TR::InstOpCode::RET.  If no epilog is generated, TR::InstOpCode::RET will stay               */
-            if (data.cursorInstruction->getOpCodeValue() != TR::InstOpCode::RET)
+            /* inserted before TR::InstOpCode::retn.  If no epilog is generated, TR::InstOpCode::retn will stay               */
+            if (data.cursorInstruction->getOpCodeValue() != TR::InstOpCode::retn)
                skipOneReturn = true;
             }
          else

diff --git a/compiler/z/codegen/OMRInstOpCode.enum b/compiler/z/codegen/OMRInstOpCode.enum
@@ -32,7 +32,6 @@
    DC2,                 // DC2
    DCB,                 // Debug Counter Bump
    DEPEND,              // Someplace to hang dependencies
-   RET,                 // Return
    VGNOP,               // ValueGuardNOP
 
    /* z900 Instructions */

diff --git a/compiler/z/codegen/OMRInstOpCodeProperties.hpp b/compiler/z/codegen/OMRInstOpCodeProperties.hpp
@@ -91,6 +91,17 @@
    /* .properties  = */ S390OpProp_None
    },
 
+   {
+   /* .mnemonic    = */ OMR::InstOpCode::retn,
+   /* .name        = */ "retn",
+   /* .description = */ "Return",
+   /* .opcode[0]   = */ 0x00,
+   /* .opcode[1]   = */ 0x00,
+   /* .format      = */ PSEUDO,
+   /* .minimumALS  = */ OMR_PROCESSOR_S390_UNKNOWN,
+   /* .properties  = */ S390OpProp_None
+   },
+
    {
    /* .mnemonic    = */ OMR::InstOpCode::BREAK,
    /* .name        = */ "BREAK",
@@ -139,17 +150,6 @@
    /* .properties  = */ S390OpProp_None
    },
 
-   {
-   /* .mnemonic    = */ OMR::InstOpCode::RET,
-   /* .name        = */ "RET",
-   /* .description = */ "Return",
-   /* .opcode[0]   = */ 0x00,
-   /* .opcode[1]   = */ 0x00,
-   /* .format      = */ PSEUDO,
-   /* .minimumALS  = */ OMR_PROCESSOR_S390_UNKNOWN,
-   /* .properties  = */ S390OpProp_None
-   },
-
    {
    /* .mnemonic    = */ OMR::InstOpCode::VGNOP,
    /* .name        = */ "VGNOP",

diff --git a/compiler/z/codegen/OMRInstruction.cpp b/compiler/z/codegen/OMRInstruction.cpp
@@ -2117,7 +2117,7 @@ OMR::Z::Instruction::is4ByteLoad()
 bool
 OMR::Z::Instruction::isRet()
    {
-   return self()->getOpCodeValue() == TR::InstOpCode::RET;
+   return self()->getOpCodeValue() == TR::InstOpCode::retn;
    }
 
 int8_t

diff --git a/compiler/z/codegen/OMRTreeEvaluator.cpp b/compiler/z/codegen/OMRTreeEvaluator.cpp
@@ -14995,7 +14995,7 @@ OMR::Z::TreeEvaluator::vreturnEvaluator(TR::Node *node, TR::CodeGenerator *cg)
    TR::RegisterDependencyConditions * dependencies = NULL ;
    dependencies= new (cg->trHeapMemory()) TR::RegisterDependencyConditions(0, 1, cg);
    dependencies->addPostCondition(returnValRegister, linkage->getVectorReturnRegister());
-   TR::Instruction * inst = generateS390PseudoInstruction(cg, TR::InstOpCode::RET, node, dependencies);
+   TR::Instruction * inst = generateS390PseudoInstruction(cg, TR::InstOpCode::retn, node, dependencies);
    cg->stopUsingRegister(returnAddressReg);
    cg->decReferenceCount(node->getFirstChild());
    return NULL ;