Remove unused pseudo-instructions on x86

The following instructions are not used anywhere in the codebase nor in any downstream projects: - VGFENCE - WRTBAR - FPREGSPILL - RestoreVMThread - PPS_OPCount - PPS_OPField
eclipse · Jun 9, 2021 · d317906 · d317906
1 parent 5849cdc
commit d317906
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Showing 7 changed files with 3 additions and 55 deletions.
diff --git a/compiler/x/codegen/OMRInstOpCode.enum b/compiler/x/codegen/OMRInstOpCode.enum
@@ -1037,15 +1037,9 @@
    VFNMSUB213SDRegRegMem,
    VFNMSUB231SDRegRegReg,
    VFNMSUB231SDRegRegMem,
-   VGFENCE,
    DQImm64,
    DDImm4,
    DWImm2,
    DBImm1,
-   WRTBAR,
-   FPREGSPILL,
    FCMPEVAL,
-   RestoreVMThread,
-   PPS_OPCount,
-   PPS_OPField,
    AdjustFramePtr,
diff --git a/compiler/x/codegen/OMRInstOpCode.enum.temp.defines b/compiler/x/codegen/OMRInstOpCode.enum.temp.defines
@@ -1025,15 +1025,9 @@
 #define   VFNMSUB213SDRegRegMem OMR::InstOpCode::VFNMSUB213SDRegRegMem
 #define   VFNMSUB231SDRegRegReg OMR::InstOpCode::VFNMSUB231SDRegRegReg
 #define   VFNMSUB231SDRegRegMem OMR::InstOpCode::VFNMSUB231SDRegRegMem
-#define   VGFENCE OMR::InstOpCode::VGFENCE
 #define   DQImm64 OMR::InstOpCode::DQImm64
 #define   DDImm4 OMR::InstOpCode::DDImm4
 #define   DWImm2 OMR::InstOpCode::DWImm2
 #define   DBImm1 OMR::InstOpCode::DBImm1
-#define   WRTBAR OMR::InstOpCode::WRTBAR
-#define   FPREGSPILL OMR::InstOpCode::FPREGSPILL
 #define   FCMPEVAL OMR::InstOpCode::FCMPEVAL
-#define   RestoreVMThread OMR::InstOpCode::RestoreVMThread
-#define   PPS_OPCount OMR::InstOpCode::PPS_OPCount
-#define   PPS_OPField OMR::InstOpCode::PPS_OPField
 #define   AdjustFramePtr OMR::InstOpCode::AdjustFramePtr
diff --git a/compiler/x/codegen/OMRInstruction.cpp b/compiler/x/codegen/OMRInstruction.cpp
@@ -73,7 +73,7 @@ OMR::X86::Instruction::initialize(TR::CodeGenerator *cg, TR::RegisterDependencyC
       {
       cond->useRegisters(self(), cg);
 
-      if (flag && op != FPREGSPILL && cg->enableRegisterAssociations())
+      if (flag && cg->enableRegisterAssociations())
          {
          cond->createRegisterAssociationDirective(self(), cg);
          }

diff --git a/compiler/x/codegen/OMRMachine.cpp b/compiler/x/codegen/OMRMachine.cpp
@@ -564,8 +564,7 @@ TR::RealRegister *OMR::X86::Machine::freeBestGPRegister(TR::Instruction
             break;
          }
 
-      if (cursor->getOpCodeValue() == TR::InstOpCode::fence ||
-          cursor->getOpCodeValue() == FPREGSPILL)
+      if (cursor->getOpCodeValue() == TR::InstOpCode::fence)
          continue;
 
       for (i = 0; i < numCandidates; i++)

diff --git a/compiler/x/codegen/OMRX86Instruction.cpp b/compiler/x/codegen/OMRX86Instruction.cpp
@@ -1331,8 +1331,7 @@ void TR::X86RegRegRegInstruction::assignRegisters(TR_RegisterKinds kindsToBeAssi
 
       if (firstRegister->decFutureUseCount() == 0                      &&
           assignedFirstRegister->getState() != TR::RealRegister::Locked &&
-          firstRegister == getTargetRegister()                         &&
-          getOpCodeValue() != WRTBAR)
+          firstRegister == getTargetRegister())
          {
          cg()->traceRegFreed(firstRegister, assignedFirstRegister);
          firstRegister->setAssignedRegister(NULL);
@@ -1423,16 +1422,6 @@ void TR::X86RegRegRegInstruction::assignRegisters(TR_RegisterKinds kindsToBeAssi
             }
          }
 
-      if (firstRegister->getFutureUseCount() == 0                      &&
-          assignedFirstRegister->getState() != TR::RealRegister::Locked &&
-          getOpCodeValue() == WRTBAR)
-         {
-         cg()->traceRegFreed(firstRegister, assignedFirstRegister);
-         firstRegister->setAssignedRegister(NULL);
-         assignedFirstRegister->setAssignedRegister(NULL);
-         assignedFirstRegister->setState(TR::RealRegister::Free);
-         }
-
       setTargetRegister(assignedFirstRegister);
       setSourceRegister(assignedSecondRegister);
       setSource2ndRegister(assignedThirdRegister);

diff --git a/compiler/x/codegen/X86Ops.ins b/compiler/x/codegen/X86Ops.ins
@@ -4084,10 +4084,6 @@ INSTRUCTION(VFNMSUB231SDRegRegMem, vfnmsub231sd,
             PROPERTY1(IA32OpProp1_XMMSource | IA32OpProp1_SourceIsMemRef | IA32OpProp1_XMMTarget)),
 
 // OpCodes beyond this point are pseudo instructions; they are for OMR internal usage only.
-INSTRUCTION(VGFENCE, VGFence, // Special Fence used for patching virtual guards
-            BINARY(VEX_L___, VEX_vNONE, PREFIX___, REX__, ESCAPE_____, 0x00, 0, ModRM_NONE, Immediate_0),
-            PROPERTY0(0),
-            PROPERTY1(IA32OpProp1_PseudoOp)),
 INSTRUCTION(DQImm64, dq, // Define 8 bytes
             BINARY(VEX_L___, VEX_vNONE, PREFIX___, REX__, ESCAPE_____, 0x00, 0, ModRM_NONE, Immediate_8),
             PROPERTY0(0),
@@ -4104,30 +4100,10 @@ INSTRUCTION(DBImm1, db, // Define 1 byte
             BINARY(VEX_L___, VEX_vNONE, PREFIX___, REX__, ESCAPE_____, 0x00, 0, ModRM_NONE, Immediate_1),
             PROPERTY0(IA32OpProp_ByteImmediate),
             PROPERTY1(IA32OpProp1_PseudoOp)),
-INSTRUCTION(WRTBAR, wrtbar, // Write barrier directive/macro for GCs that need them
-            BINARY(VEX_L___, VEX_vNONE, PREFIX___, REX__, ESCAPE_____, 0x00, 0, ModRM_NONE, Immediate_0),
-            PROPERTY0(IA32OpProp_UsesTarget | IA32OpProp_ModifiesTarget | IA32OpProp_IntSource | IA32OpProp_IntTarget | IA32OpProp_ByteTarget),
-            PROPERTY1(IA32OpProp1_PseudoOp)),
-INSTRUCTION(FPREGSPILL, fpRegSpill, // Directive to force the FP stack to be spilled
-            BINARY(VEX_L___, VEX_vNONE, PREFIX___, REX__, ESCAPE_____, 0x00, 0, ModRM_NONE, Immediate_0),
-            PROPERTY0(0),
-            PROPERTY1(IA32OpProp1_PseudoOp)),
 INSTRUCTION(FCMPEVAL, fcmpEval, // Instruction selection of FP comparisons at register assignment time
             BINARY(VEX_L___, VEX_vNONE, PREFIX___, REX__, ESCAPE_____, 0x00, 0, ModRM_NONE, Immediate_0),
             PROPERTY0(0),
             PROPERTY1(IA32OpProp1_PseudoOp)),
-INSTRUCTION(RestoreVMThread, RestoreVMThread, // restore VM thread register from fs:[0]
-            BINARY(VEX_L___, VEX_vNONE, PREFIX___, REX__, ESCAPE_____, 0x00, 0, ModRM_NONE, Immediate_0),
-            PROPERTY0(0),
-            PROPERTY1(IA32OpProp1_PseudoOp)),
-INSTRUCTION(PPS_OPCount, PPS_OPCount, // Phase profiling site (object access counting)
-            BINARY(VEX_L___, VEX_vNONE, PREFIX___, REX__, ESCAPE_____, 0x00, 0, ModRM_NONE, Immediate_0),
-            PROPERTY0(IA32OpProp_UsesTarget | IA32OpProp_ModifiesOverflowFlag | IA32OpProp_ModifiesSignFlag | IA32OpProp_ModifiesZeroFlag | IA32OpProp_ModifiesParityFlag | IA32OpProp_ModifiesCarryFlag),
-            PROPERTY1(IA32OpProp1_PseudoOp)),
-INSTRUCTION(PPS_OPField, PPS_OPField, // Phase profiling site (object field counting)
-            BINARY(VEX_L___, VEX_vNONE, PREFIX___, REX__, ESCAPE_____, 0x00, 0, ModRM_NONE, Immediate_0),
-            PROPERTY0(IA32OpProp_ModifiesOverflowFlag | IA32OpProp_ModifiesSignFlag | IA32OpProp_ModifiesZeroFlag | IA32OpProp_ModifiesParityFlag | IA32OpProp_ModifiesCarryFlag),
-            PROPERTY1(IA32OpProp1_PseudoOp)),
 INSTRUCTION(AdjustFramePtr, AdjustFramePtr, // Adjust frame pointer
             BINARY(VEX_L___, VEX_vNONE, PREFIX___, REX__, ESCAPE_____, 0x00, 0, ModRM_NONE, Immediate_0),
             PROPERTY0(0),

diff --git a/compiler/x/i386/codegen/IA32SystemLinkage.cpp b/compiler/x/i386/codegen/IA32SystemLinkage.cpp
@@ -306,10 +306,6 @@ TR::IA32SystemLinkage::buildVolatileAndReturnDependencies(
       {
       deps->addPostCondition(returnReg, _properties.getFloatReturnRegister(), cg());
       }
-   else
-      {
-      // No need for a dummy dep here because FPREGSPILL instruction takes care of it
-      }
 
  // The reg dependency is left open intentionally, and need to be closed by
  // the caller. The reason is because, child class might call this method, while