Use common proc instruction on ARM

eclipse · Jun 15, 2021 · e054445 · e054445
1 parent 54e8adb
commit e054445
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Showing 5 changed files with 3 additions and 9 deletions.
diff --git a/compiler/arm/codegen/OMRCodeGenerator.cpp b/compiler/arm/codegen/OMRCodeGenerator.cpp
@@ -330,13 +330,13 @@ void OMR::ARM::CodeGenerator::beginInstructionSelection()
          }
 
       _returnTypeInfoInstruction = new (self()->trHeapMemory()) TR::ARMImmInstruction(cursor, TR::InstOpCode::dd, startNode, 0, self());
-      new (self()->trHeapMemory()) TR::ARMAdminInstruction(_returnTypeInfoInstruction, ARMOp_proc, startNode, NULL, self());
+      new (self()->trHeapMemory()) TR::ARMAdminInstruction(_returnTypeInfoInstruction, TR::InstOpCode::proc, startNode, NULL, self());
 
       }
    else
       {
       _returnTypeInfoInstruction = NULL;
-      new (self()->trHeapMemory()) TR::ARMAdminInstruction((TR::Instruction *)NULL, ARMOp_proc, startNode, NULL, self());
+      new (self()->trHeapMemory()) TR::ARMAdminInstruction((TR::Instruction *)NULL, TR::InstOpCode::proc, startNode, NULL, self());
       }
    }
 

diff --git a/compiler/arm/codegen/OMRInstOpCode.cpp b/compiler/arm/codegen/OMRInstOpCode.cpp
@@ -101,7 +101,6 @@ const OMR::ARM::InstOpCode::TR_OpCodeBinaryEntry OMR::ARM::InstOpCode::binaryEnc
    0x06FF0070,  // uxth
    0x00000000,  // ret
    0x00000000,  // wrtbar
-   0x00000000,  // proc
    0x0E070FBA,  // dmb_v6
    0xF57FF05F,  // dmb
    0xF57FF05E,  // dmb_st
@@ -398,9 +397,6 @@ ARMOpProp_Arch4,
 // wrtbar
 0,
 
-// proc
-0,
-
 // dmb_v6
 0,
 

diff --git a/compiler/arm/codegen/OMRInstOpCode.enum b/compiler/arm/codegen/OMRInstOpCode.enum
@@ -91,7 +91,6 @@
    ARMOp_uxth,             // Zero extend halfword
    ARMOp_ret,              // Return
    ARMOp_wrtbar,           // Write barrier directive
-   ARMOp_proc,             // Entry to the method
    ARMOp_dmb_v6,           // Data memory barrier
    ARMOp_dmb,              // Data memory barrier on ARMv7A
    ARMOp_dmb_st,           // Data write memory barrier on ARMv7A

diff --git a/compiler/arm/codegen/OMRInstOpCode.enum.temp.defines b/compiler/arm/codegen/OMRInstOpCode.enum.temp.defines
@@ -89,7 +89,6 @@
 #define ARMOp_uxth OMR::InstOpCode::ARMOp_uxth
 #define ARMOp_ret OMR::InstOpCode::ARMOp_ret
 #define ARMOp_wrtbar OMR::InstOpCode::ARMOp_wrtbar
-#define ARMOp_proc OMR::InstOpCode::ARMOp_proc
 #define ARMOp_dmb_v6 OMR::InstOpCode::ARMOp_dmb_v6
 #define ARMOp_dmb OMR::InstOpCode::ARMOp_dmb
 #define ARMOp_dmb_st OMR::InstOpCode::ARMOp_dmb_st

diff --git a/compiler/arm/codegen/OMRMachine.cpp b/compiler/arm/codegen/OMRMachine.cpp
@@ -158,7 +158,7 @@ TR::RealRegister *OMR::ARM::Machine::freeBestRegister(TR::Instruction     *curre
       while (numCandidates > 1                 &&
              cursor != NULL                    &&
              cursor->getOpCodeValue() != TR::InstOpCode::label &&
-             cursor->getOpCodeValue() != ARMOp_proc)
+             cursor->getOpCodeValue() != TR::InstOpCode::proc)
          {
          for (int i = 0; i < numCandidates; i++)
             {