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Migrate label to the common codegen
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@fjeremic
fjeremic committed May 12, 2021
1 parent 8d698eb commit e62f3d2
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Showing 28 changed files with 294 additions and 298 deletions.
2 changes: 1 addition & 1 deletion compiler/aarch64/codegen/ARM64Debug.cpp
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Expand Up @@ -97,6 +97,7 @@ static const char *opCodeToNameMap[] =
"bad",
"dd",
"fence",
"label",
"cbzw",
"cbnzw",
"cbzx",
Expand Down Expand Up @@ -750,7 +751,6 @@ static const char *opCodeToNameMap[] =
"nop",
"proc",
"return",
"label",
"vgdnop",
};

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1 change: 0 additions & 1 deletion compiler/aarch64/codegen/OMRInstOpCode.enum
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Expand Up @@ -735,7 +735,6 @@
/* Internal OpCodes */
proc, // Entry to the method
retn, // Return
label, // Destination of a jump
vgdnop, // Virtual Guard NOP instruction
ARM64LastOp = vgdnop,
ARM64NumOpCodes = ARM64LastOp+1,
3 changes: 2 additions & 1 deletion compiler/codegen/OMRInstOpCode.enum
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Expand Up @@ -27,4 +27,5 @@
assocreg, // Register Association
bad, // Bad Opcode
dd, // Define Doubleword
fence, // Fence
fence, // Fence
label, // Destination of a jump
1 change: 0 additions & 1 deletion compiler/p/codegen/OMRInstOpCode.enum
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Expand Up @@ -1067,7 +1067,6 @@
xvrsqrtesp, // Vector Reciprocal Square Root Estimate Single-Precision
xvsqrtsp, // Vector Square Root Single-Precision
xvsubsp, // Vector Subtract Single-Precision
label, // Destination of a jump
brd, // Byte-Reverse Doubleword
brh, // Byte-Reverse Halfword
brw, // Byte-Reverse Word
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23 changes: 11 additions & 12 deletions compiler/p/codegen/OMRInstOpCodeProperties.hpp
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Expand Up @@ -69,6 +69,17 @@
/* .properties = */ PPCOpProp_SyncSideEffectFree,
},

{
/* .mnemonic = */ OMR::InstOpCode::label,
/* .name = */ "label",
/* .description = "Destination of a jump", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x00000000,
/* .format = */ FORMAT_NONE,
/* .minimumALS = */ OMR_PROCESSOR_PPC_UNKNOWN,
/* .properties = */ PPCOpProp_None,
},

{
/* .mnemonic = */ OMR::InstOpCode::add,
/* .name = */ "add",
Expand Down Expand Up @@ -12752,18 +12763,6 @@
PPCOpProp_SyncSideEffectFree,
},

{
/* .mnemonic = */ OMR::InstOpCode::label,
/* .name = */ "label",
/* .description = "Destination of a jump", */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x00000000,
/* .format = */ FORMAT_NONE,
/* .minimumALS = */ OMR_PROCESSOR_PPC_UNKNOWN,
/* .properties = */ PPCOpProp_None,
},


{
/* .mnemonic = */ OMR::InstOpCode::brd,
/* .name = */ "brd",
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3 changes: 1 addition & 2 deletions compiler/riscv/codegen/OMRInstOpCode.enum
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Expand Up @@ -35,6 +35,5 @@
/* Internal OpCodes */
proc, // Entry to the method
retn, // Return
label, // Destination of a jump
RVLastOp = label,
RVLastOp = retn,
RVNumOpCodes = RVLastOp+1,
2 changes: 1 addition & 1 deletion compiler/riscv/codegen/RVDebug.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -43,6 +43,7 @@ static const char *opCodeToNameMap[] =
"bad",
"dd",
"fence",
"label",
/*
* RISC-V instructions
*/
Expand All @@ -51,7 +52,6 @@ static const char *opCodeToNameMap[] =
#undef DECLARE_INSN
"proc",
"return",
"label"
};

const char *
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2 changes: 1 addition & 1 deletion compiler/z/codegen/BinaryCommutativeAnalyser.cpp
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Expand Up @@ -915,7 +915,7 @@ TR_S390BinaryCommutativeAnalyser::integerAddAnalyser(TR::Node * root, TR::InstOp
}

//if (hasCompressedPointers)
// generateS390LabelInstruction(cg(), TR::InstOpCode::LABEL, root, skipAdd);
// generateS390LabelInstruction(cg(), TR::InstOpCode::label, root, skipAdd);

cg()->decReferenceCount(firstChild);
cg()->decReferenceCount(secondChild);
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74 changes: 37 additions & 37 deletions compiler/z/codegen/BinaryEvaluator.cpp
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6 changes: 3 additions & 3 deletions compiler/z/codegen/CompareAnalyser.cpp
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Expand Up @@ -294,7 +294,7 @@ TR_S390CompareAnalyser::longOrderedCompareAndBranchAnalyser(TR::Node * root, TR:
TR::LabelSymbol * cflowRegionStart = generateLabelSymbol(_cg);
cflowRegionStart->setStartInternalControlFlow();
internalControlFlowStarted = true;
generateS390LabelInstruction(_cg, TR::InstOpCode::LABEL, root, cflowRegionStart);
generateS390LabelInstruction(_cg, TR::InstOpCode::label, root, cflowRegionStart);

// See if we can prove results as false
if (brCmpHighFalseCond != TR::InstOpCode::COND_NOP)
Expand Down Expand Up @@ -404,7 +404,7 @@ TR_S390CompareAnalyser::longOrderedCompareAndBranchAnalyser(TR::Node * root, TR:
TR::LabelSymbol * cflowRegionStart = generateLabelSymbol(_cg);
cflowRegionStart->setStartInternalControlFlow();
internalControlFlowStarted = true;
generateS390LabelInstruction(_cg, TR::InstOpCode::LABEL, root, cflowRegionStart);
generateS390LabelInstruction(_cg, TR::InstOpCode::label, root, cflowRegionStart);

// See if we can prove results as false
if (brCmpHighFalseCond != TR::InstOpCode::COND_NOP)
Expand Down Expand Up @@ -511,7 +511,7 @@ TR_S390CompareAnalyser::longOrderedCompareAndBranchAnalyser(TR::Node * root, TR:
TR::LabelSymbol * cflowRegionStart = generateLabelSymbol(_cg);
cflowRegionStart->setStartInternalControlFlow();
internalControlFlowStarted = true;
generateS390LabelInstruction(_cg, TR::InstOpCode::LABEL, root, cflowRegionStart);
generateS390LabelInstruction(_cg, TR::InstOpCode::label, root, cflowRegionStart);

// See if we can prove results as false
if (brCmpHighFalseCond != TR::InstOpCode::COND_NOP)
Expand Down
42 changes: 21 additions & 21 deletions compiler/z/codegen/ControlFlowEvaluator.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -224,7 +224,7 @@ generateS390lcmpEvaluator64(TR::Node * node, TR::CodeGenerator * cg, TR::InstOpC
int64_t long_value = secondChild->getLongInt();
TR::Register * cmpRegister = cg->evaluate(firstChild);
generateS390ImmOp(cg, isUnsigned ? TR::InstOpCode::CLG : TR::InstOpCode::CG, node, cmpRegister, cmpRegister, long_value);
generateS390LabelInstruction(cg, TR::InstOpCode::LABEL, node, cFlowRegionStart);
generateS390LabelInstruction(cg, TR::InstOpCode::label, node, cFlowRegionStart);
generateS390BranchInstruction(cg, brOp, brCond, node, isTrue);
}
else
Expand All @@ -236,7 +236,7 @@ generateS390lcmpEvaluator64(TR::Node * node, TR::CodeGenerator * cg, TR::InstOpC
deps = new (cg->trHeapMemory()) TR::RegisterDependencyConditions(0, 3, cg);
deps->addPostConditionIfNotAlreadyInserted(cmpRegister,TR::RealRegister::AssignAny);
deps->addPostConditionIfNotAlreadyInserted(srcReg,TR::RealRegister::AssignAny);
generateS390LabelInstruction(cg, TR::InstOpCode::LABEL, node, cFlowRegionStart);
generateS390LabelInstruction(cg, TR::InstOpCode::label, node, cFlowRegionStart);
generateS390CompareAndBranchInstruction(cg, isUnsigned ? TR::InstOpCode::CLGR : TR::InstOpCode::CGR, node, cmpRegister, srcReg, brCond, isTrue, false, false);
}

Expand All @@ -246,7 +246,7 @@ generateS390lcmpEvaluator64(TR::Node * node, TR::CodeGenerator * cg, TR::InstOpC
// FALSE
genLoadLongConstant(cg, node, 0, targetRegister);
// TRUE
generateS390LabelInstruction(cg, TR::InstOpCode::LABEL, node, isTrue, deps);
generateS390LabelInstruction(cg, TR::InstOpCode::label, node, isTrue, deps);
isTrue->setEndInternalControlFlow();

node->setRegister(targetRegister);
Expand Down Expand Up @@ -286,7 +286,7 @@ OMR::Z::TreeEvaluator::fcmplEvaluator(TR::Node * node, TR::CodeGenerator * cg)
TR::RegisterDependencyConditions *deps = new (cg->trHeapMemory()) TR::RegisterDependencyConditions(0, 1, cg);
deps->addPostCondition(targetRegister,TR::RealRegister::AssignAny);

generateS390LabelInstruction(cg, TR::InstOpCode::LABEL, node, cFlowRegionStart);
generateS390LabelInstruction(cg, TR::InstOpCode::label, node, cFlowRegionStart);
cFlowRegionStart->setStartInternalControlFlow();
generateS390BranchInstruction(cg, TR::InstOpCode::BRC, TR::InstOpCode::COND_BE, node, cFlowRegionEnd);

Expand All @@ -308,7 +308,7 @@ OMR::Z::TreeEvaluator::fcmplEvaluator(TR::Node * node, TR::CodeGenerator * cg)
generateLoad32BitConstant(cg, node, -1, targetRegister, true);

// DONE
generateS390LabelInstruction(cg, TR::InstOpCode::LABEL, node, cFlowRegionEnd, deps);
generateS390LabelInstruction(cg, TR::InstOpCode::label, node, cFlowRegionEnd, deps);
cFlowRegionEnd->setEndInternalControlFlow();

node->setRegister(targetRegister);
Expand All @@ -335,7 +335,7 @@ xmaxxminHelper(TR::Node* node, TR::CodeGenerator* cg, TR::InstOpCode::Mnemonic c
TR::LabelSymbol* cFlowRegionStart = generateLabelSymbol(cg);
TR::LabelSymbol* cFlowRegionEnd = generateLabelSymbol(cg);

generateS390LabelInstruction(cg, TR::InstOpCode::LABEL, node, cFlowRegionStart);
generateS390LabelInstruction(cg, TR::InstOpCode::label, node, cFlowRegionStart);
cFlowRegionStart->setStartInternalControlFlow();

generateRREInstruction(cg, compareRROp, node, lhsReg, rhsReg);
Expand All @@ -348,7 +348,7 @@ xmaxxminHelper(TR::Node* node, TR::CodeGenerator* cg, TR::InstOpCode::Mnemonic c
deps->addPostConditionIfNotAlreadyInserted(lhsReg, TR::RealRegister::AssignAny);
deps->addPostConditionIfNotAlreadyInserted(rhsReg, TR::RealRegister::AssignAny);

generateS390LabelInstruction(cg, TR::InstOpCode::LABEL, node, cFlowRegionEnd, deps);
generateS390LabelInstruction(cg, TR::InstOpCode::label, node, cFlowRegionEnd, deps);
cFlowRegionEnd->setEndInternalControlFlow();

node->setRegister(lhsReg);
Expand Down Expand Up @@ -553,7 +553,7 @@ lcmpHelper64(TR::Node * node, TR::CodeGenerator * cg)
generateRRInstruction(cg, TR::InstOpCode::CGR, node, src1Reg, src2Reg);
}
// If LT we are done
generateS390LabelInstruction(cg, TR::InstOpCode::LABEL, node, cFlowRegionStart);
generateS390LabelInstruction(cg, TR::InstOpCode::label, node, cFlowRegionStart);
cFlowRegionStart->setStartInternalControlFlow();
generateS390BranchInstruction(cg, TR::InstOpCode::BRC, TR::InstOpCode::COND_BL, node, labelLT);

Expand All @@ -566,14 +566,14 @@ lcmpHelper64(TR::Node * node, TR::CodeGenerator * cg)

// We can go through this path if GT, or if EQ.
// We use LCR to avoid having to branch over this piece of code.
generateS390LabelInstruction(cg, TR::InstOpCode::LABEL, node, labelGT);
generateS390LabelInstruction(cg, TR::InstOpCode::label, node, labelGT);
generateRRInstruction(cg, TR::InstOpCode::LCGR, node, targetRegister, targetRegister);

// We branch here when LT (no change to assumed -1 result)
TR::RegisterDependencyConditions * dependencies = NULL;
dependencies = new (cg->trHeapMemory()) TR::RegisterDependencyConditions(0, 1, cg);
dependencies->addPostCondition(targetRegister, TR::RealRegister::AssignAny);
generateS390LabelInstruction(cg, TR::InstOpCode::LABEL, node, labelLT, dependencies);
generateS390LabelInstruction(cg, TR::InstOpCode::label, node, labelLT, dependencies);
labelLT->setEndInternalControlFlow();
}

Expand Down Expand Up @@ -820,7 +820,7 @@ static inline void generateMergedGuardCodeIfNeeded(TR::Node *node, TR::CodeGener
TR::Instruction *vgnopInstr = generateVirtualGuardNOPInstruction(cg, node, site, deps, fallThroughLabel, instr ? instr->getPrev() : NULL);
vgnopInstr->setNext(instr);
cg->setAppendInstruction(instr);
generateS390LabelInstruction(cg, TR::InstOpCode::LABEL, node, fallThroughLabel, mergedGuardDeps);
generateS390LabelInstruction(cg, TR::InstOpCode::label, node, fallThroughLabel, mergedGuardDeps);
}
else
{
Expand Down Expand Up @@ -1882,7 +1882,7 @@ OMR::Z::TreeEvaluator::lookupEvaluator(TR::Node * node, TR::CodeGenerator * cg)
if (type.isInt64() && cg->comp()->target().is32Bit())
{
cursor = generateS390BranchInstruction(cg, TR::InstOpCode::BRC, brCond, node, child->getBranchDestination()->getNode()->getLabel());
generateS390LabelInstruction(cg, TR::InstOpCode::LABEL, node, skipLoCompareLabel, generateRegisterDependencyConditions(cg, child->getFirstChild(), 0), cursor);
generateS390LabelInstruction(cg, TR::InstOpCode::label, node, skipLoCompareLabel, generateRegisterDependencyConditions(cg, child->getFirstChild(), 0), cursor);
}
else
cursor = generateS390BranchInstruction(cg, TR::InstOpCode::BRC, brCond, node, child->getBranchDestination()->getNode()->getLabel(),
Expand All @@ -1892,7 +1892,7 @@ OMR::Z::TreeEvaluator::lookupEvaluator(TR::Node * node, TR::CodeGenerator * cg)
{
cursor = generateS390BranchInstruction(cg, TR::InstOpCode::BRC, brCond, node, child->getBranchDestination()->getNode()->getLabel());
if (type.isInt64() && cg->comp()->target().is32Bit())
generateS390LabelInstruction(cg, TR::InstOpCode::LABEL, node, skipLoCompareLabel);
generateS390LabelInstruction(cg, TR::InstOpCode::label, node, skipLoCompareLabel);
}

}
Expand Down Expand Up @@ -1955,7 +1955,7 @@ OMR::Z::TreeEvaluator::ZEROCHKEvaluator(TR::Node * node, TR::CodeGenerator * cg)
}

// Outlined instructions for check failure
TR::Instruction * cursor = generateS390LabelInstruction(cg, TR::InstOpCode::LABEL, node, slowPathOOLLabel);
TR::Instruction * cursor = generateS390LabelInstruction(cg, TR::InstOpCode::label, node, slowPathOOLLabel);

// For helper call, we need to pass the 2nd and any successive children as
// parameters. Temporarily hide the first child so it doesn't appear in the
Expand All @@ -1976,7 +1976,7 @@ OMR::Z::TreeEvaluator::ZEROCHKEvaluator(TR::Node * node, TR::CodeGenerator * cg)
cg->recursivelyDecReferenceCount(node->getChild(i));

// Merge Point back from OOL to mainline.
generateS390LabelInstruction(cg, TR::InstOpCode::LABEL, node, doneLabel);
generateS390LabelInstruction(cg, TR::InstOpCode::label, node, doneLabel);

// We only need to decrement the first child, as 2nd and successive children
cg->decReferenceCount(node->getFirstChild());
Expand Down Expand Up @@ -2553,7 +2553,7 @@ OMR::Z::TreeEvaluator::selectEvaluator(TR::Node *node, TR::CodeGenerator *cg)
TR::LabelSymbol * cFlowRegionStart = generateLabelSymbol( cg);
TR::LabelSymbol * cFlowRegionEnd = generateLabelSymbol( cg);

generateS390LabelInstruction(cg, TR::InstOpCode::LABEL, node, cFlowRegionStart);
generateS390LabelInstruction(cg, TR::InstOpCode::label, node, cFlowRegionStart);
cFlowRegionStart->setStartInternalControlFlow();
generateS390CompareAndBranchInstruction(cg, compareOp, node, firstReg, secondReg, bc, cFlowRegionEnd, false);

Expand All @@ -2578,7 +2578,7 @@ OMR::Z::TreeEvaluator::selectEvaluator(TR::Node *node, TR::CodeGenerator *cg)

generateRRInstruction(cg, trueVal->getOpCode().is8Byte() ? TR::InstOpCode::LGR : TR::InstOpCode::LR, node, trueReg, falseReg);

generateS390LabelInstruction(cg, TR::InstOpCode::LABEL, node, cFlowRegionEnd, conditions);
generateS390LabelInstruction(cg, TR::InstOpCode::label, node, cFlowRegionEnd, conditions);
cFlowRegionEnd->setEndInternalControlFlow();

if (comp->getOption(TR_TraceCG))
Expand Down Expand Up @@ -2617,7 +2617,7 @@ OMR::Z::TreeEvaluator::selectEvaluator(TR::Node *node, TR::CodeGenerator *cg)
TR::LabelSymbol * cFlowRegionStart = generateLabelSymbol( cg);
TR::LabelSymbol * cFlowRegionEnd = generateLabelSymbol( cg);

generateS390LabelInstruction(cg, TR::InstOpCode::LABEL, node, cFlowRegionStart);
generateS390LabelInstruction(cg, TR::InstOpCode::label, node, cFlowRegionStart);
cFlowRegionStart->setStartInternalControlFlow();
TR::Instruction *branchInst = generateS390BranchInstruction(cg, TR::InstOpCode::BRC, TR::InstOpCode::COND_BNE, node, cFlowRegionEnd);

Expand All @@ -2637,7 +2637,7 @@ OMR::Z::TreeEvaluator::selectEvaluator(TR::Node *node, TR::CodeGenerator *cg)

generateRRInstruction(cg, trueVal->getOpCode().is8Byte() ? TR::InstOpCode::LGR : TR::InstOpCode::LR, node, trueReg, falseReg);

generateS390LabelInstruction(cg, TR::InstOpCode::LABEL, node, cFlowRegionEnd, conditions);
generateS390LabelInstruction(cg, TR::InstOpCode::label, node, cFlowRegionEnd, conditions);
cFlowRegionEnd->setEndInternalControlFlow();
}
}
Expand Down Expand Up @@ -2685,14 +2685,14 @@ OMR::Z::TreeEvaluator::dselectEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::LabelSymbol *cFlowRegionEnd = generateLabelSymbol(cg);
TR::LabelSymbol *cFlowRegionStart = generateLabelSymbol(cg);
generateS390LabelInstruction(cg, TR::InstOpCode::LABEL, node , cFlowRegionStart);
generateS390LabelInstruction(cg, TR::InstOpCode::label, node , cFlowRegionStart);
TR::RegisterDependencyConditions* conditions = new (cg->trHeapMemory()) TR::RegisterDependencyConditions(0, 3, cg);
conditions->addPostCondition(resultReg, TR::RealRegister::AssignAny);
conditions->addPostCondition(falseValReg, TR::RealRegister::AssignAny);
conditions->addPostCondition(conditionReg, TR::RealRegister::AssignAny);
generateS390CompareAndBranchInstruction(cg, TR::InstOpCode::CL, node, conditionReg, 0, TR::InstOpCode::COND_BNE, cFlowRegionEnd, false, false);
generateRRInstruction(cg, node->getOpCode().isDouble() ? TR::InstOpCode::LDR : TR::InstOpCode::LER, node, resultReg, falseValReg);
generateS390LabelInstruction(cg, TR::InstOpCode::LABEL, node, cFlowRegionEnd, conditions);
generateS390LabelInstruction(cg, TR::InstOpCode::label, node, cFlowRegionEnd, conditions);
cFlowRegionStart->setStartInternalControlFlow();
cFlowRegionEnd->setEndInternalControlFlow();
}
Expand Down
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