Perform better spill placement for GPRs only on x86 #6598
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Signed-off-by: BradleyWood <bradley.wood@ibm.com>
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Jenkins build xlinux,x32linux |
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Can you create an issue to track implementing BSP for non-GPR register kinds? The optimization is sound for non-GPR kinds even if the current implementation needs some work in order to support it. |
0xdaryl
reviewed
Jul 6, 2022
| @@ -1209,6 +1209,10 @@ void OMR::X86::CodeGenerator::saveBetterSpillPlacements(TR::Instruction * branch | |||
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| void OMR::X86::CodeGenerator::removeBetterSpillPlacementCandidate(TR::RealRegister * realReg) | |||
| { | |||
| // this mechanism only supports GPR's | |||
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Can you drop a sentence in here explaining why so it is clear to others coming across this code? (presumably interference with the register mask)
0xdaryl
reviewed
Jul 6, 2022
| @@ -1250,6 +1254,11 @@ OMR::X86::CodeGenerator::findBetterSpillPlacement( | |||
| { | |||
| TR::Instruction * placement; | |||
| TR_BetterSpillPlacement * info; | |||
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| // this mechanism only supports GPR's | |||
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Same comment as above for providing an explanation.
Signed-off-by: BradleyWood <bradley.wood@ibm.com>
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Jenkins build xlinux,win,osx,x32linux |
0xdaryl
approved these changes
Jul 15, 2022
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Jenkins build xlinux,x32linux
See #6602