Procesador-Monociclo-VHDL

Procesador monociclo en VHDL basado en la arquitectura RISC de 32 bits

Name		Name	Last commit message	Last commit date
Latest commit History 5 Commits
ALU.vhd		ALU.vhd
ControlALU.vhd		ControlALU.vhd
ControlUnit.vhd		ControlUnit.vhd
DataMemory.vhd		DataMemory.vhd
InstructionMemory.vhd		InstructionMemory.vhd
MuxALU.vhd		MuxALU.vhd
MuxPC.vhd		MuxPC.vhd
MuxRF.vhd		MuxRF.vhd
README.md		README.md
RegisterFile.vhd		RegisterFile.vhd
SignExtend.vhd		SignExtend.vhd
tb_ALU.vhd		tb_ALU.vhd
tb_ControlALU.vhd		tb_ControlALU.vhd
tb_ControlUnit.vhd		tb_ControlUnit.vhd
tb_DataMemory.vhd		tb_DataMemory.vhd
tb_InstructionMemory.vhd		tb_InstructionMemory.vhd
tb_MuxALU.vhd		tb_MuxALU.vhd
tb_MuxPC.vhd		tb_MuxPC.vhd
tb_MuxRF.vhd		tb_MuxRF.vhd
tb_RegisterFile.vhd		tb_RegisterFile.vhd
tb_SignExtend.vhd		tb_SignExtend.vhd

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