Implicit wires and default_nettype

[olofk]

Working on packaging caravel-lite with FuseSoC with first objective to run the caravel tests with FuseSoC using different simulators. Currently, only icarus works since other simulators require module ports to explciitly specify wire in addition to direction when used with defualt_netttype none. Modelsim is also not too happy about mixing port styles (although there is a -mixedansiports that helps to some extent.

I have started to manually change to explicit wires in all the verilog files and got some simulations running with both xsim and modelsim but before doing too much work I would just like to ask

1. Is this repo intended to replace caravel or is my efforts better spent on the caravel repo?
2. Are you open to accept such a change?

[Manarabdelaty]

1. This repo is automatically updated when we push to caravel master, so no development is done here.
2. I think this PR seems relevant to your issue update gpio control block caravel#57

[olofk]

Great. Thanks for the info. Yes, this is very much related. I'll close this and look into the linked issue