Fix issues with port definitions

[antonblanchard]

Caravel fails to build with recent Icarus Verilog versions because some of the port definitions are not valid.

[RTimothyEdwards]

But I've been using the original syntax for years---there's nothing wrong with it, and it has no errors with other tools that read verilog. The problem is in iverilog. Version 13 has broken something.

[larsclausen]

If the ports are specified in parenthesis (called ANSI-style) after the module name this is not valid. If the ports are specified inside the module body (called non-ANSI style) it is valid.

// Invalid
module test(input i);
  wire i;
endmodule

// Valid
module test;
  input i;
  wire i;
endmodule

Both the Verilog and SystemVerilog reference manuals explicitly call this out.

Each port declaration provides the complete information about the port. The port’s direction, width, net or
variable type, and signedness are completely described. The port identifier shall not be redeclared, in part or
in full, inside the module body.

But considering that there is code that uses this, it might make sense to add a switch to iverilog to allow this as an anachronism.

[antonblanchard]

@RTimothyEdwards

But I've been using the original syntax for years---there's nothing wrong with it, and it has no errors with other tools that read verilog. The problem is in iverilog. Version 13 has broken something.

This syntax also fails on Verilator, so it makes sense to merge this regardless of if iverilog adds a flag.

[RTimothyEdwards]

The syntax restriction is so stupidly unnecessary, it amazes me that any tool would fail to just parse this code correctly. But whatever.

[RTimothyEdwards]

@jeffdi : Please merge this.

[mattvenn]

Is anyone still hitting this? It still seems to be an issue.
`When you change to the test directory: verilog/dv/io_ports

and run make

You get the following error when you are using the latest version of iverilog (as distributed with the OSS_CAD_Suite
Icarus Verilog version 13.0)

/root/eda//caravel_user_project/verilog/rtl/user_proj_example.v:74: error: 'io_in' has already been declared in this scope.
/root/eda//caravel_user_project/verilog/rtl/user_proj_example.v:64: : It was declared here as a net.
/root/eda//caravel_user_project/verilog/rtl/user_proj_example.v:75: error: 'io_out' has already been declared in this scope.
/root/eda//caravel_user_project/verilog/rtl/user_proj_example.v:65: : It was declared here as a net.
/root/eda//caravel_user_project/verilog/rtl/user_proj_example.v:76: error: 'io_oeb' has already been declared in this scope.
/root/eda//caravel_user_project/verilog/rtl/user_proj_example.v:66: : It was declared here as a net.
/root/eda//caravel_user_project/verilog/rtl/user_proj_example.v:138: error: 'ready' has already been declared in this scope.
/root/eda//caravel_user_project/verilog/rtl/user_proj_example.v:134: : It was declared here as a net.
/root/eda//caravel_user_project/verilog/rtl/user_proj_example.v:139: error: 'count' has already been declared in this scope.
/root/eda//caravel_user_project/verilog/rtl/user_proj_example.v:136: : It was declared here as a net.
/root/eda//caravel_user_project/verilog/rtl/user_proj_example.v:140: error: 'rdata' has already been declared in this scope.
/root/eda//caravel_user_project/verilog/rtl/user_proj_example.v:135: : It was declared here as a net.`