More STM32F030 words

ekoeppen · Feb 20, 2014 · 8159a37 · 8159a37
1 parent 74990e7
commit 8159a37
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Showing 2 changed files with 91 additions and 48 deletions.
diff --git a/generic/CoreForth.s b/generic/CoreForth.s
@@ -16,7 +16,7 @@
     .set link_host,            0
     .set ram_here, ram_start
 
-    .set FEATURE_COMPILER, 1
+    .set ENABLE_COMPILER, 1
 
 @ ---------------------------------------------------------------------
 @ -- Macros -----------------------------------------------------------
@@ -1289,9 +1289,13 @@ is_positive:
     bkpt 0xab
     NEXT
 
+    target_conditional ENABLE_NEVER
+
     defword "ROM-DUMP", ROM_DUMP
     .word LIT, _start, ROM_DP, FETCH, LIT, 0x80, EMULATOR_BKPT, EXIT
 
+    end_target_conditional
+
     defword "BYE", BYE
     .word LIT, 0x18, EMULATOR_BKPT, EXIT
 
@@ -1411,7 +1415,7 @@ is_positive:
     adds r1, r1, #1
     mov pc, r1
 
-    target_conditional FEATURE_COMPILER
+    target_conditional ENABLE_COMPILER
 
     defword "MARKER", MARKER, 0X0
     .word CREATE, LATEST, FETCH, FETCH, COMMA, LPARENDOESGTRPAREN
@@ -1528,23 +1532,6 @@ interpret_not_found:
 interpret_eol:
     .word LIT, -1, EXIT
 
-    defword "EVALUATE", EVALUATE
-    .word XSOURCE, STORE
-    .word LIT, 0, STATE, STORE
-1:  .word XSOURCE, FETCH
-5:  .word DUP, FETCHBYTE, DUP, ZNEQU, QBRANCH, 2f - ., LIT, 10, EQU, QBRANCH, 7f - .
-    .word INCR, BRANCH, 5b - .
-7:  .word DUP
-6:  .word DUP, FETCHBYTE, LIT, 10, NEQU, QBRANCH, 4f - .
-    .word INCR, BRANCH, 6b - .
-4:  .word OVER, SUB
-    .word TWODUP, TYPE, CR
-    .word SOURCECOUNT, STORE, XSOURCE, STORE, LIT, 0, SOURCEINDEX, STORE
-    .word XINTERPRET, QBRANCH, 3f - ., DROP
-    .word SOURCECOUNT, FETCH, XSOURCE, ADDSTORE, BRANCH, 1b - .
-2:  .word DROP, EXIT
-3:  .word DROP, DUP, DOT, SPACE, COUNT, TYPE, LIT, '?', EMIT, CR, EXIT
-
     defword "FORGET", FORGET
     .word BL, WORD, FIND, DROP, TOLINK, FETCH, LATEST, STORE, EXIT
 
@@ -1571,6 +1558,27 @@ interpret_eol:
 
     end_target_conditional
 
+    target_conditional ENABLE_EVALUATE
+
+    defword "EVALUATE", EVALUATE
+    .word XSOURCE, STORE
+    .word LIT, 0, STATE, STORE
+1:  .word XSOURCE, FETCH
+5:  .word DUP, FETCHBYTE, DUP, ZNEQU, QBRANCH, 2f - ., LIT, 10, EQU, QBRANCH, 7f - .
+    .word INCR, BRANCH, 5b - .
+7:  .word DUP
+6:  .word DUP, FETCHBYTE, LIT, 10, NEQU, QBRANCH, 4f - .
+    .word INCR, BRANCH, 6b - .
+4:  .word OVER, SUB
+    .word TWODUP, TYPE, CR
+    .word SOURCECOUNT, STORE, XSOURCE, STORE, LIT, 0, SOURCEINDEX, STORE
+    .word XINTERPRET, QBRANCH, 3f - ., DROP
+    .word SOURCECOUNT, FETCH, XSOURCE, ADDSTORE, BRANCH, 1b - .
+2:  .word DROP, EXIT
+3:  .word DROP, DUP, DOT, SPACE, COUNT, TYPE, LIT, '?', EMIT, CR, EXIT
+
+    end_target_conditional
+
     defword "WORDS", WORDS
     .word LATEST, FETCH
 words_loop:

diff --git a/stm32f030/stm32f030.ft b/stm32f030/stm32f030.ft
@@ -31,45 +31,80 @@ HEX
 28 REGISTER GPIO-BRR
 
 40021000 CONSTANT RCC
-00 REGISTER RCC-CR
-04 REGISTER RCC-CFGR
-08 REGISTER RCC-CIR
-0C REGISTER RCC-APB2RSTR
-10 REGISTER RCC-APB1RSTR
-14 REGISTER RCC-AHBENR
-18 REGISTER RCC-APB2ENR
-1C REGISTER RCC-APB1ENR
-20 REGISTER RCC-BDCR
-24 REGISTER RCC-CSR
-28 REGISTER RCC-AHBRSTR
-2C REGISTER RCC-CFGR2
+40021000 CONSTANT RCC-CR
+40021004 CONSTANT RCC-CFGR
+40021008 CONSTANT RCC-CIR
+4002100C CONSTANT RCC-APB2RSTR
+40021010 CONSTANT RCC-APB1RSTR
+40021014 CONSTANT RCC-AHBENR
+40021018 CONSTANT RCC-APB2ENR
+4002101C CONSTANT RCC-APB1ENR
+40021020 CONSTANT RCC-BDCR
+40021024 CONSTANT RCC-CSR
+40021028 CONSTANT RCC-AHBRSTR
+4002102C CONSTANT RCC-CFGR2
 
 40012400 CONSTANT ADC
-00 REGISTER ADC-ISR
-04 REGISTER ADC-IER
-08 REGISTER ADC-CR
-0C REGISTER ADC-CFGR1
-10 REGISTER ADC-CFGR2
-14 REGISTER ADC-SMPR
-20 REGISTER ADC-TR
-28 REGISTER ADC-CHSELR
-40 REGISTER ADC-DR
-308 REGISTER ADC-CCR
+40012400 CONSTANT ADC-ISR
+40012404 CONSTANT ADC-IER
+40012408 CONSTANT ADC-CR
+4001240C CONSTANT ADC-CFGR1
+40012410 CONSTANT ADC-CFGR2
+40012414 CONSTANT ADC-SMPR
+40012420 CONSTANT ADC-TR
+40012428 CONSTANT ADC-CHSELR
+40012440 CONSTANT ADC-DR
+40012708 CONSTANT ADC-CCR
+
+40010000 CONSTANT SYSCFG
+40010000 CONSTANT SYSCFG-CFGR1
+40010008 CONSTANT SYSCFG-EXTICR1
+4001000C CONSTANT SYSCFG-EXTICR2
+40010010 CONSTANT SYSCFG-EXTICR3
+40010014 CONSTANT SYSCFG-EXTICR4
+40010018 CONSTANT SYSCFG-CFGR2
+
+40010400 CONSTANT EXTI
+40010400 CONSTANT EXTI-IMR
+40010400 CONSTANT EXTI-EMR
+40010400 CONSTANT EXTI-RTSR
+40010400 CONSTANT EXTI-FTSR
+40010400 CONSTANT EXTI-SWIER
+40010400 CONSTANT EXTI-PR
+
+0E000E000 CONSTANT NVIC
+0E000E100 CONSTANT NVIC-SETENA-BASE
+0E000E180 CONSTANT NVIC-CLRENA-BASE
+0E000E200 CONSTANT NVIC-SETPEND-BASE
+0E000E280 CONSTANT NVIC-CLRPEND-BASE
+0E000E300 CONSTANT NVIC-ACTIVE-BASE
+0E000E400 CONSTANT NVIC-PRI-BASE
+
+40007000 CONSTANT PWR
+40007000 CONSTANT PWR-CR
+40007004 CONSTANT PWR-CSR
+
+40002800 CONSTANT RTC
 
 : ADC-ENABLE
-   200 RCC RCC-APB2ENR SET-BITS
-   1 ADC ADC-CR SET-BITS
+   200 RCC-APB2ENR SET-BITS
+   1 ADC-CR SET-BITS
 ;
 
 : ADC-SAMPLE
-   1 SWAP ROTATE ADC ADC-CHSELR !
-   4 ADC ADC-CR SET-BITS
-   ADC DUP ADC-ISR BEGIN DUP @ 4 AND UNTIL DROP ADC-DR @
+   1 SWAP ROTATE ADC-CHSELR !
+   4 ADC-CR SET-BITS
+   ADC-ISR BEGIN DUP @ 4 AND UNTIL DROP ADC-DR @
 ;
 
 : ADC-DISABLE
-   0 ADC ADC-CR !
-   200 RCC RCC-APB2ENR CLEAR-BITS
+   0 ADC-CR !
+   200 RCC-APB2ENR CLEAR-BITS
+;
+
+: SYSCFG-ENABLE
+   1 RCC-APB2ENR SET-BITS
 ;
 
 : TURNKEY   HEX ABORT ;
+