Verilog-Learning

This repo documents the learning of verilog HDL from various resources

Folder	Description
Logic_Gates	Modelling Logic Equations using logic gates

Name		Name	Last commit message	Last commit date
Latest commit History 39 Commits
Adder_Subtractor		Adder_Subtractor
Clock_Dividers		Clock_Dividers
Combinational		Combinational
Comparators		Comparators
Counters		Counters
Edge_Detectors		Edge_Detectors
Encoder_Decoder		Encoder_Decoder
FSMs		FSMs
Latches_Flip_Flop		Latches_Flip_Flop
Logic_Gates		Logic_Gates
Multiplier		Multiplier
Mux_Demux		Mux_Demux
Operators		Operators
Resets		Resets
Shift_Registers		Shift_Registers
System_Tasks		System_Tasks
Tasks_and_Functions		Tasks_and_Functions
README.md		README.md

embedded-explorer/Verilog-Learning