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embedded-explorer/README.md
  • 👋 Hi, This is Hrishikesh
  • 👀 VLSI Enthusiast
  • 🌱 Working on RTL design for FPGAs
  • 💞️ I’m looking to collaborate projects invloving RTL design using verilog

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  1. Open-Source-RTL-Design Open-Source-RTL-Design Public

    This repository documents the learning from VSD "RTL Design Using Verilog With SKY130 Technology" workshop

    Verilog 31 7

  2. Verilog-Learning Verilog-Learning Public

    This repo documents the learning of verilog HDL from various resources

    Verilog 3

  3. System-Verilog-Learning System-Verilog-Learning Public

    System-Verilog Design Examples along with Complete Verification Environment

    SystemVerilog

  4. UART-Implementation UART-Implementation Public

    Documents implementation of UART Controller using System-Verilog and Testing using Arty-S7 FPGA

    SystemVerilog