Local interrupts work and handled.

embeddedden · Jul 9, 2017 · 1aa5dfa · 1aa5dfa
1 parent f394233
commit 1aa5dfa
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Showing 2 changed files with 30 additions and 16 deletions.
diff --git a/c/src/lib/libbsp/riscv32/hifive1/irq/irq.c b/c/src/lib/libbsp/riscv32/hifive1/irq/irq.c
@@ -80,7 +80,8 @@ static uint32_t cntr = 0;
 static uint32_t cntr1 = 0;
 static uint32_t cntr2 = 0;
 static uint32_t excep = 0; 
-static uint32_t times[10];
+static uint64_t times[10] = {0};
+static uint64_t cmprs[10] = {0};
 
 void handle_trap_new ()
 {
@@ -93,22 +94,26 @@ void handle_trap_new ()
     volatile uint64_t * mtime = (uint64_t *)0x0200bff8;
     if (cause & MCAUSE_INT) { 
       /* an interrupt occurred */
-      if (cause & MCAUSE_MTIME) {
+      if ((cause & MCAUSE_MTIME) == MCAUSE_MTIME) {
 	/* Timer interrupt */
 	asm volatile ("csrci mie, 0x80");
 	asm volatile ("csrr %0, mie": "=r" (mie));
 	asm volatile ("csrr %0, mip": "=r" (mip));
-	volatile uint64_t * mtimecmp = (uint64_t *)0x02004000;
-	*mtimecmp = *mtime + 0x300;
-        if (cntr < 10) 
+        volatile uint64_t * mtimecmp = (uint64_t *)0x02004000;
+	if (cntr < 10) {
 	  times[cntr] = *mtime;
+	  cmprs[cntr] = *mtimecmp;
+	}
+
+	(*mtimecmp) = (*mtime) + 0x300;
+
 	cntr++;
         asm volatile ("csrsi mie, 0x80");
         asm volatile ("csrr %0, mip": "=r" (mip));	
-      } else if (cause & MCAUSE_MEXT) {
+      } else if ((cause & MCAUSE_MEXT) == MCAUSE_MEXT) {
 	/*External interrupt */
         cntr1 += 1;
-      } else if (cause & MCAUSE_MSWI) {
+      } else if ((cause & MCAUSE_MSWI) == MCAUSE_MSWI) {
 	/* Software interrupt */
 	volatile uint32_t * msip_reg = 0x02000000;
 	*msip_reg = 0;

diff --git a/c/src/lib/libbsp/riscv32/hifive1/start/start.S b/c/src/lib/libbsp/riscv32/hifive1/start/start.S
@@ -122,21 +122,22 @@ _loop_copy_data:
 _end_copy_data:
 
 
-/* Enable interrupts in mie register (not enabled in mstatus yet) */
-  la t0, RISCV_Exception_default
-  csrs mtvec, t0
-  li t0, 0x88
-  csrs mie, t0
-  csrsi mstatus, 0x8
 
 
 irq_gen:
-  sw t0, 0(t1)
+/*  sw t0, 0(t1) */
   li t2, MTIME_REG
-  li t4, 0x1
+  li t4, 0x300
   lw t0, 0(t2)
   add t0, t0, t4
-  li t3, MTIMECMP
+  li t3, MTIMECMP 
+  sw t0, 0(t3)
+
+/* copy MSB of mtime */
+  addi t3, t3, 4
+  addi t2, t2, 4
+/* race condition may arise here */
+  lw t0, 0(t2)
   sw t0, 0(t3)
 
   li t3, 0x02000000
@@ -145,6 +146,12 @@ irq_gen:
   nop
 
 
+/* Enable interrupts in mie register (not enabled in mstatus yet) */
+  la t0, RISCV_Exception_default
+  csrw mtvec, t0
+  li t0, 0x88
+  csrs mie, t0
+  csrsi mstatus, 0x8
 
   call boot_card
   nop
@@ -187,6 +194,7 @@ SYM(RISCV_Exception_default):
   nop
 trap_entry:
 	nop
+  csrci mstatus, 0x8
   addi sp, sp, -32*REGBYTES
   SREG x1, 1*REGBYTES(sp)
   SREG x2, 2*REGBYTES(sp)
@@ -263,5 +271,6 @@ trap_entry:
   LREG x31, 31*REGBYTES(sp) 
 
   addi sp, sp, 32*REGBYTES
+  csrsi mstatus, 0x8
 
   mret