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phy/xilinx_us: Update from xilinx_usp changes.
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@enjoy-digital
enjoy-digital committed Nov 9, 2023
1 parent 8d0d012 commit 796c3dd
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Showing 9 changed files with 396 additions and 405 deletions.
50 changes: 24 additions & 26 deletions litepcie/phy/xilinx_us/m_axis_cq_adapt_x4.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -64,7 +64,7 @@ module m_axis_cq_adapt # (
else if (m_axis_cq_tlast_lat && m_axis_cq_tready) m_axis_cq_tlast_lat <= 1'd0;
else if (m_axis_cq_tvalid_a && m_axis_cq_tready_a && m_axis_cq_tlast_a)
begin
if (m_axis_cq_sop) m_axis_cq_tlast_lat <= 1'b1; //read
if (m_axis_cq_sop) m_axis_cq_tlast_lat <= 1'd1; //read
else if (m_axis_cq_tlast_dly_en) m_axis_cq_tlast_lat <= 1'b1;
end

Expand All @@ -77,8 +77,8 @@ module m_axis_cq_adapt # (


////keep address (low) or data (high), not header
reg [DATA_WIDTH-1:0] m_axis_cq_tdata_a1;
reg [DATA_WIDTH/8-1:0] m_axis_cq_tlast_be1;
reg [127:0] m_axis_cq_tdata_a1;
reg [15:0] m_axis_cq_tlast_be1;
always @(posedge user_clk)
if (m_axis_cq_tvalid_a && m_axis_cq_tready_a)
begin
Expand All @@ -89,15 +89,15 @@ module m_axis_cq_adapt # (
//data processing
wire [63:0] m_axis_cq_tdata_hdr = m_axis_cq_tdata_a[127:64];

assign m_axis_cq_dwlen = m_axis_cq_tdata_hdr[9:0];
wire [1:0] m_axis_cq_attr = m_axis_cq_tdata_hdr[61:60];
wire m_axis_cq_ep = 1'b0;
wire m_axis_cq_td = 1'b0;
wire [2:0] m_axis_cq_tc = m_axis_cq_tdata_hdr[59:57];
assign m_axis_cq_dwlen = m_axis_cq_tdata_hdr[9:0];
wire [1:0] m_axis_cq_attr = m_axis_cq_tdata_hdr[61:60];
wire m_axis_cq_ep = 1'b0;
wire m_axis_cq_td = 1'b0;
wire [2:0] m_axis_cq_tc = m_axis_cq_tdata_hdr[59:57];
wire [4:0] m_axis_cq_type;
wire [2:0] m_axis_cq_fmt;
wire [7:0] m_axis_cq_be = m_axis_cq_tuser_a[7:0];
wire [7:0] m_axis_cq_tag = m_axis_cq_tdata_hdr[39:32];
wire [7:0] m_axis_cq_be = m_axis_cq_tuser_a[7:0];
wire [7:0] m_axis_cq_tag = m_axis_cq_tdata_hdr[39:32];
wire [15:0] m_axis_cq_requesterid = m_axis_cq_tdata_hdr[31:16];

assign {m_axis_cq_fmt, m_axis_cq_type} = m_axis_cq_tdata_hdr[14:11] == 4'b0000 ? 8'b000_00000 : //Mem read Request
Expand Down Expand Up @@ -125,15 +125,13 @@ module m_axis_cq_adapt # (
reg [63:0] m_axis_cq_header;
always @(posedge user_clk)
if (m_axis_cq_tvalid_a && m_axis_cq_sop)
m_axis_cq_header = {
m_axis_cq_requesterid,
m_axis_cq_tag,
m_axis_cq_be,
m_axis_cq_fmt, m_axis_cq_type,
1'b0, m_axis_cq_tc, 4'b0,
m_axis_cq_td, m_axis_cq_ep, m_axis_cq_attr,
2'b0, m_axis_cq_dwlen
};
m_axis_cq_header = {m_axis_cq_requesterid,
m_axis_cq_tag,
m_axis_cq_be,
m_axis_cq_fmt, m_axis_cq_type,
1'b0, m_axis_cq_tc, 4'b0,
m_axis_cq_td, m_axis_cq_ep, m_axis_cq_attr,
2'b0, m_axis_cq_dwlen};

wire [31:0] m_axis_cq_hiaddr_mask = m_axis_cq_read_l ? 32'b0 : m_axis_cq_tdata_a[31:0];
assign m_axis_cq_tdata = (m_axis_cq_read_l | m_axis_cq_second) ? {m_axis_cq_hiaddr_mask, m_axis_cq_tdata_a1[31:0], m_axis_cq_header} :
Expand All @@ -144,12 +142,12 @@ module m_axis_cq_adapt # (


assign m_axis_cq_tuser = {
5'b0, //rx_is_eof only for 128-bit I/F
2'b0, //reserved
5'b0, //m_axis_cq_tuser_a[40],4'b0, //rx_is_sof only for 128-bit I/F
m_axis_cq_tuser_barhit,
1'b0, //rx_err_fwd -> no equivalent
m_axis_cq_ecrc //ECRC mapped to discontinue
};
5'b0, //rx_is_eof only for 128-bit I/F
2'b0, //reserved
5'b0, //m_axis_cq_tuser_a[40],4'b0, //rx_is_sof only for 128-bit I/F
m_axis_cq_tuser_barhit,
1'b0, //rx_err_fwd -> no equivalent
m_axis_cq_ecrc //ECRC mapped to discontinue
};

endmodule
52 changes: 25 additions & 27 deletions litepcie/phy/xilinx_us/m_axis_cq_adapt_x8.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@
// SPDX-License-Identifier: BSD-2-Clause

module m_axis_cq_adapt # (
parameter DATA_WIDTH = 128,
parameter DATA_WIDTH = 256,
parameter KEEP_WIDTH = DATA_WIDTH/8
)(

Expand Down Expand Up @@ -60,7 +60,7 @@ module m_axis_cq_adapt # (
else if (m_axis_cq_tlast_lat && m_axis_cq_tready) m_axis_cq_tlast_lat <= 1'd0;
else if (m_axis_cq_tvalid_a && m_axis_cq_tready_a && m_axis_cq_tlast_a)
begin
if (m_axis_cq_sop) m_axis_cq_tlast_lat <= 1'b1; //read
if (m_axis_cq_sop) m_axis_cq_tlast_lat <= 1'b1;
else if (m_axis_cq_tlast_dly_en) m_axis_cq_tlast_lat <= 1'b1;
end

Expand All @@ -73,8 +73,8 @@ module m_axis_cq_adapt # (


////keep address (low) or data (high), not header
reg [DATA_WIDTH-1:0] m_axis_cq_tdata_a1;
reg [DATA_WIDTH/8-1:0] m_axis_cq_tlast_be1;
reg [255:0] m_axis_cq_tdata_a1;
reg [31:0] m_axis_cq_tlast_be1;
always @(posedge user_clk)
if (m_axis_cq_tvalid_a && m_axis_cq_tready_a)
begin
Expand All @@ -85,15 +85,15 @@ module m_axis_cq_adapt # (
//data processing
wire [63:0] m_axis_cq_tdata_hdr = m_axis_cq_tdata_a[127:64];

assign m_axis_cq_dwlen = m_axis_cq_tdata_hdr[9:0];
wire [1:0] m_axis_cq_attr = m_axis_cq_tdata_hdr[61:60];
wire m_axis_cq_ep = 1'b0;
wire m_axis_cq_td = 1'b0;
wire [2:0] m_axis_cq_tc = m_axis_cq_tdata_hdr[59:57];
assign m_axis_cq_dwlen = m_axis_cq_tdata_hdr[9:0];
wire [1:0] m_axis_cq_attr = m_axis_cq_tdata_hdr[61:60];
wire m_axis_cq_ep = 1'b0;
wire m_axis_cq_td = 1'b0;
wire [2:0] m_axis_cq_tc = m_axis_cq_tdata_hdr[59:57];
wire [4:0] m_axis_cq_type;
wire [2:0] m_axis_cq_fmt;
wire [7:0] m_axis_cq_be = m_axis_cq_tuser_a[7:0];
wire [7:0] m_axis_cq_tag = m_axis_cq_tdata_hdr[39:32];
wire [7:0] m_axis_cq_be = m_axis_cq_tuser_a[7:0];
wire [7:0] m_axis_cq_tag = m_axis_cq_tdata_hdr[39:32];
wire [15:0] m_axis_cq_requesterid = m_axis_cq_tdata_hdr[31:16];

assign {m_axis_cq_fmt, m_axis_cq_type} = m_axis_cq_tdata_hdr[14:11] == 4'b0000 ? 8'b000_00000 : //Mem read Request
Expand All @@ -115,27 +115,25 @@ module m_axis_cq_adapt # (
reg [63:0] m_axis_cq_header;
always @(posedge user_clk)
if (m_axis_cq_tvalid_a && m_axis_cq_sop)
m_axis_cq_header = {
m_axis_cq_requesterid,
m_axis_cq_tag,
m_axis_cq_be,
m_axis_cq_fmt, m_axis_cq_type,
1'b0, m_axis_cq_tc, 4'b0,
m_axis_cq_td, m_axis_cq_ep, m_axis_cq_attr,
2'b0, m_axis_cq_dwlen
};
m_axis_cq_header = {m_axis_cq_requesterid,
m_axis_cq_tag,
m_axis_cq_be,
m_axis_cq_fmt, m_axis_cq_type,
1'b0, m_axis_cq_tc, 4'b0,
m_axis_cq_td, m_axis_cq_ep, m_axis_cq_attr,
2'b0, m_axis_cq_dwlen};

assign m_axis_cq_tdata = (m_axis_cq_rdwr_l | m_axis_cq_second) ? {m_axis_cq_tdata_a[31:0], m_axis_cq_tdata_a1[255:128], m_axis_cq_tdata_a1[31:0], m_axis_cq_header} :
{m_axis_cq_tdata_a[31:0], m_axis_cq_tdata_a1[255:32]};
assign m_axis_cq_tkeep = m_axis_cq_rdwr_l ? {4'b0, m_axis_cq_tlast_be1[31:16], 12'hFFF} :
m_axis_cq_tlast_lat ? {4'b0, m_axis_cq_tlast_be1[31:4]} : 32'hFFFF_FFFF;
assign m_axis_cq_tuser = {
5'b0, //rx_is_eof only for 128-bit I/F
2'b0, //reserved
5'b0, //m_axis_cq_tuser_a[40],4'b0, //rx_is_sof only for 128-bit I/F
m_axis_cq_tuser_barhit,
1'b0, //rx_err_fwd -> no equivalent
m_axis_cq_tuser_a[41] //ECRC mapped to discontinue
};
5'b0, //rx_is_eof only for 128-bit I/F
2'b0, //reserved
5'b0, //m_axis_cq_tuser_a[40],4'b0, //rx_is_sof only for 128-bit I/F
m_axis_cq_tuser_barhit,
1'b0, //rx_err_fwd -> no equivalent
m_axis_cq_tuser_a[41] //ECRC mapped to discontinue
};

endmodule
75 changes: 35 additions & 40 deletions litepcie/phy/xilinx_us/m_axis_rc_adapt_x4.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -47,20 +47,20 @@ module m_axis_rc_adapt # (
m_axis_rc_poisoning_l <= m_axis_rc_poisoning;
end

wire [9:0] m_axis_rc_dwlen = m_axis_rc_tdata_a[41:32];
wire [1:0] m_axis_rc_attr = m_axis_rc_tdata_a[93:92];
wire m_axis_rc_ep = 1'b0;
wire m_axis_rc_td = 1'b0;
wire [2:0] m_axis_rc_tc = m_axis_rc_tdata_a[91:89];
wire [9:0] m_axis_rc_dwlen = m_axis_rc_tdata_a[41:32];
wire [1:0] m_axis_rc_attr = m_axis_rc_tdata_a[93:92];
wire m_axis_rc_ep = 1'b0;
wire m_axis_rc_td = 1'b0;
wire [2:0] m_axis_rc_tc = m_axis_rc_tdata_a[91:89];
wire [4:0] m_axis_rc_type;
wire [2:0] m_axis_rc_fmt;
wire [11:0] m_axis_rc_bytecnt = m_axis_rc_tdata_a[27:16];
wire m_axis_rc_bmc = 1'b0;
wire [2:0] m_axis_rc_cmpstatus = m_axis_rc_tdata_a[45:43];
wire [11:0] m_axis_rc_bytecnt = m_axis_rc_tdata_a[27:16];
wire m_axis_rc_bmc = 1'b0;
wire [2:0] m_axis_rc_cmpstatus = m_axis_rc_tdata_a[45:43];
wire [15:0] m_axis_rc_completerid = m_axis_rc_tdata_a[87:72];

wire [6:0] m_axis_rc_lowaddr = m_axis_rc_tdata_a[6:0];
wire [7:0] m_axis_rc_tag = m_axis_rc_tdata_a[71:64];
wire [6:0] m_axis_rc_lowaddr = m_axis_rc_tdata_a[6:0];
wire [7:0] m_axis_rc_tag = m_axis_rc_tdata_a[71:64];
wire [15:0] m_axis_rc_requesterid = m_axis_rc_tdata_a[63:48];

assign {m_axis_rc_fmt,
Expand All @@ -69,36 +69,31 @@ module m_axis_rc_adapt # (
((m_axis_rc_bytecnt == 0) ? 8'b000_01010 : //Completion w/o data
8'b010_01010); //Completion w/ data

wire [63:0] m_axis_rc_header0 = {
m_axis_rc_completerid,
m_axis_rc_cmpstatus,
m_axis_rc_bmc,
m_axis_rc_bytecnt,
m_axis_rc_fmt[2:0], m_axis_rc_type,
1'b0, m_axis_rc_tc, 4'b0,
m_axis_rc_td, m_axis_rc_ep, m_axis_rc_attr,
2'b0, m_axis_rc_dwlen
};
wire [63:0] m_axis_rc_header1 = {
m_axis_rc_tdata_a[127:96],
m_axis_rc_requesterid,
m_axis_rc_tag,
1'b0, m_axis_rc_lowaddr
};

assign m_axis_rc_tvalid = m_axis_rc_tvalid_a;
assign m_axis_rc_tready_a = m_axis_rc_tready;
assign m_axis_rc_tlast = m_axis_rc_tlast_a;
assign m_axis_rc_tdata = m_axis_rc_sop ? {m_axis_rc_header1, m_axis_rc_header0} : m_axis_rc_tdata_a;
assign m_axis_rc_tkeep = m_axis_rc_sop ? 16'hFFFF : m_axis_rc_tuser_a[15:0];
assign m_axis_rc_tuser = {
5'd0, //m_axis_rc_tlast_a, 4'b0, //rx_is_eof only for 128-bit I/F
2'b0, //reserved
m_axis_rc_sop, 4'b0, //m_axis_rc_tuser_a[32],4'b0, //rx_is_sof, only for 128-bit I/F ??????
8'b0, //BAR hit no equivalent for RC
m_axis_rc_sop ? m_axis_rc_poisoning : m_axis_rc_poisoning_l, //rx_err_fwd mapped to Poisoned completion
m_axis_rc_tuser_a[42] //ECRC mapped to discontinue
};
wire [63:0] m_axis_rc_header0 = {m_axis_rc_completerid,
m_axis_rc_cmpstatus,
m_axis_rc_bmc,
m_axis_rc_bytecnt,
m_axis_rc_fmt[2:0], m_axis_rc_type,
1'b0, m_axis_rc_tc, 4'b0,
m_axis_rc_td, m_axis_rc_ep, m_axis_rc_attr,
2'b0, m_axis_rc_dwlen};
wire [63:0] m_axis_rc_header1 = {m_axis_rc_tdata_a[127:96],
m_axis_rc_requesterid,
m_axis_rc_tag,
1'b0, m_axis_rc_lowaddr};

assign m_axis_rc_tvalid = m_axis_rc_tvalid_a;
assign m_axis_rc_tready_a = m_axis_rc_tready;
assign m_axis_rc_tlast = m_axis_rc_tlast_a;
assign m_axis_rc_tdata = m_axis_rc_sop ? {m_axis_rc_header1, m_axis_rc_header0} : m_axis_rc_tdata_a;
assign m_axis_rc_tkeep = m_axis_rc_sop ? 16'hFFFF : m_axis_rc_tuser_a[15:0];
assign m_axis_rc_tuser = {
5'd0, //m_axis_rc_tlast_a, 4'b0, //rx_is_eof only for 128-bit I/F
2'b0, //reserved
m_axis_rc_sop, 4'b0, //m_axis_rc_tuser_a[32],4'b0, //rx_is_sof, only for 128-bit I/F ?????????????????????
8'b0, //BAR hit no equivalent for RC
m_axis_rc_sop ? m_axis_rc_poisoning : m_axis_rc_poisoning_l, //rx_err_fwd mapped to Poisoned completion
m_axis_rc_tuser_a[42] //ECRC mapped to discontinue
};

endmodule
77 changes: 37 additions & 40 deletions litepcie/phy/xilinx_us/m_axis_rc_adapt_x8.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@
// SPDX-License-Identifier: BSD-2-Clause

module m_axis_rc_adapt # (
parameter DATA_WIDTH = 128,
parameter DATA_WIDTH = 256,
parameter KEEP_WIDTH = DATA_WIDTH/8
)(

Expand Down Expand Up @@ -47,20 +47,20 @@ module m_axis_rc_adapt # (
m_axis_rc_poisoning_l <= m_axis_rc_poisoning;
end

wire [9:0] m_axis_rc_dwlen = m_axis_rc_tdata_a[41:32];
wire [1:0] m_axis_rc_attr = m_axis_rc_tdata_a[93:92];
wire m_axis_rc_ep = 1'b0;
wire m_axis_rc_td = 1'b0;
wire [2:0] m_axis_rc_tc = m_axis_rc_tdata_a[91:89];
wire [9:0] m_axis_rc_dwlen = m_axis_rc_tdata_a[41:32];
wire [1:0] m_axis_rc_attr = m_axis_rc_tdata_a[93:92];
wire m_axis_rc_ep = 1'b0;
wire m_axis_rc_td = 1'b0;
wire [2:0] m_axis_rc_tc = m_axis_rc_tdata_a[91:89];
wire [4:0] m_axis_rc_type;
wire [2:0] m_axis_rc_fmt;
wire [11:0] m_axis_rc_bytecnt = m_axis_rc_tdata_a[27:16];
wire m_axis_rc_bmc = 1'b0;
wire [2:0] m_axis_rc_cmpstatus = m_axis_rc_tdata_a[45:43];
wire [11:0] m_axis_rc_bytecnt = m_axis_rc_tdata_a[27:16];
wire m_axis_rc_bmc = 1'b0;
wire [2:0] m_axis_rc_cmpstatus = m_axis_rc_tdata_a[45:43];
wire [15:0] m_axis_rc_completerid = m_axis_rc_tdata_a[87:72];

wire [6:0] m_axis_rc_lowaddr = m_axis_rc_tdata_a[6:0];
wire [7:0] m_axis_rc_tag = m_axis_rc_tdata_a[71:64];
wire [6:0] m_axis_rc_lowaddr = m_axis_rc_tdata_a[6:0];
wire [7:0] m_axis_rc_tag = m_axis_rc_tdata_a[71:64];
wire [15:0] m_axis_rc_requesterid = m_axis_rc_tdata_a[63:48];

assign {m_axis_rc_fmt,
Expand All @@ -69,35 +69,32 @@ module m_axis_rc_adapt # (
((m_axis_rc_bytecnt == 0) ? 8'b000_01010 : //Completion w/o data
8'b010_01010); //Completion w/ data

wire [63:0] m_axis_rc_header0 = {
m_axis_rc_completerid,
m_axis_rc_cmpstatus,
m_axis_rc_bmc,
m_axis_rc_bytecnt,
m_axis_rc_fmt[2:0], m_axis_rc_type,
1'b0, m_axis_rc_tc, 4'b0,
m_axis_rc_td, m_axis_rc_ep, m_axis_rc_attr,
2'b0, m_axis_rc_dwlen
};
wire [63:0] m_axis_rc_header1 = {
m_axis_rc_tdata_a[127:96],
m_axis_rc_requesterid,
m_axis_rc_tag,
1'b0, m_axis_rc_lowaddr
};
wire [63:0] m_axis_rc_header0 = {m_axis_rc_completerid,
m_axis_rc_cmpstatus,
m_axis_rc_bmc,
m_axis_rc_bytecnt,
m_axis_rc_fmt[2:0], m_axis_rc_type,
1'b0, m_axis_rc_tc, 4'b0,
m_axis_rc_td, m_axis_rc_ep, m_axis_rc_attr,
2'b0, m_axis_rc_dwlen};
wire [63:0] m_axis_rc_header1 = {m_axis_rc_tdata_a[127:96],
m_axis_rc_requesterid,
m_axis_rc_tag,
1'b0, m_axis_rc_lowaddr};

assign m_axis_rc_tvalid = m_axis_rc_tvalid_a;
assign m_axis_rc_tready_a = m_axis_rc_tready;
assign m_axis_rc_tlast = m_axis_rc_tlast_a;
assign m_axis_rc_tdata = m_axis_rc_sop ? {m_axis_rc_tdata_a[255:128], m_axis_rc_header1, m_axis_rc_header0} : m_axis_rc_tdata_a;
assign m_axis_rc_tkeep = m_axis_rc_sop ? {m_axis_rc_tuser_a[31:12], 12'hFFF} : m_axis_rc_tuser_a[31:0];
assign m_axis_rc_tuser = {
5'b0, //rx_is_eof only for 128-bit I/F
2'b0, //reserved
5'b0, //m_axis_rc_tuser_a[32],4'b0, //rx_is_sof, only for 128-bit I/F ?????????????????????
8'b0, //BAR hit no equivalent for RC
m_axis_rc_sop ? m_axis_rc_poisoning : m_axis_rc_poisoning_l, //rx_err_fwd mapped to Poisoned completion
m_axis_rc_tuser_a[42] //ECRC mapped to discontinue
};

assign m_axis_rc_tvalid = m_axis_rc_tvalid_a;
assign m_axis_rc_tready_a = m_axis_rc_tready;
assign m_axis_rc_tlast = m_axis_rc_tlast_a;
assign m_axis_rc_tdata = m_axis_rc_sop ? {m_axis_rc_tdata_a[255:128], m_axis_rc_header1, m_axis_rc_header0} : m_axis_rc_tdata_a;
assign m_axis_rc_tkeep = m_axis_rc_sop ? {m_axis_rc_tuser_a[31:12], 12'hFFF} : m_axis_rc_tuser_a[31:0];
assign m_axis_rc_tuser = {
5'b0, //rx_is_eof only for 128-bit I/F
2'b0, //reserved
5'b0, //m_axis_rc_tuser_a[32],4'b0, //rx_is_sof, only for 128-bit I/F ?????????????????????
8'b0, //BAR hit no equivalent for RC
m_axis_rc_sop ? m_axis_rc_poisoning : m_axis_rc_poisoning_l, //rx_err_fwd mapped to Poisoned completion
m_axis_rc_tuser_a[42] //ECRC mapped to discontinue
};

endmodule
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