register liteuart for crossover UART

[sergachev]

Addressing #35 - now one gets working /dev/ttyLXU0 if CSR_UART_XOVER_RXTX_ADDR was defined and when liteuart module is loaded.

liteuart from the mainline kernel temporarily added here with a few changes:

• few bugs were found in liteuart_probe() and liteuart_remove() - one by me, other ones by Johan Hovold - that's now under review in LKML
• for me writes to OFF_EV_PENDING during read were causing missing symbols - comparing to litepcie_util uart_test() I removed it and now it works fine; not sure if that is really needed when the driver is used on a "real" SoC
• on a "real" SoC the driver gets a memory region resource and this way the base offset, but in this use case it just needs an offset inside PCIe BAR0 - so I modified probe() to accept register resource optionally like some other drivers do

liteuart and litepcie can be loaded and unloaded in any order. One can build the driver with make CFLAGS_MODULE=-DCONFIG_SERIAL_LITEUART_MAX_PORTS=1 - most systems will not have CONFIG_SERIAL_LITEUART_MAX_PORTS defined.

Tested on hardware with this SoC project: https://github.com/sergachev/litepcie_acorn

[mithro]

FYI - @kgugala / @shenki

[enjoy-digital]

Thanks a lot @sergachev, this was the missing piece to be able to have the FPGA board in the PCIe slot without requiring external cables :): https://twitter.com/enjoy_digital/status/1461353848388284422

This is working fine and I'm going to merge it. I would just like for now to keep compatibility with older kernels (Older than the initial LiteX drivers merge and initial platform_get_mem_or_io addition) so will just do minor changes.

[enjoy-digital]

@sergachev: I just added these changes on top of yours:

• 60e03fb
• 963165f