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phy: Add buffers on SDPHYDATAW/R datapaths to improve timings.
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enjoy-digital committed Nov 7, 2023
1 parent 3c9b241 commit 8f15cbe
Showing 1 changed file with 16 additions and 2 deletions.
18 changes: 16 additions & 2 deletions litesdcard/phy.py
Original file line number Diff line number Diff line change
Expand Up @@ -315,7 +315,7 @@ def __init__(self, sys_clk_freq, cmd_timeout, cmdw, busy_timeout=1):
# SDCard PHY Data Write ----------------------------------------------------------------------------

class SDPHYDATAW(LiteXModule):
def __init__(self):
def __init__(self, with_data_buffer=True):
self.pads_in = pads_in = stream.Endpoint(_sdpads_layout)
self.pads_out = pads_out = stream.Endpoint(_sdpads_layout)
self.sink = sink = stream.Endpoint([("data", 8)])
Expand All @@ -329,6 +329,13 @@ def __init__(self):

# # #

if with_data_buffer:
assert sink is self.sink
self.data_buffer = stream.Buffer([("data", 8)], pipe_valid=True, pipe_ready=True)
self.comb += self.sink.connect(self.data_buffer.sink)
sink = self.data_buffer.source
assert sink is not self.sink

count = Signal(8)

accepted = Signal()
Expand Down Expand Up @@ -421,7 +428,7 @@ def __init__(self):
# SDCard PHY Data Read -----------------------------------------------------------------------------

class SDPHYDATAR(LiteXModule):
def __init__(self, sys_clk_freq, data_timeout):
def __init__(self, sys_clk_freq, data_timeout, with_data_buffer=True):
self.pads_in = pads_in = stream.Endpoint(_sdpads_layout)
self.pads_out = pads_out = stream.Endpoint(_sdpads_layout)
self.sink = sink = stream.Endpoint([("block_length", 10)])
Expand All @@ -430,6 +437,13 @@ def __init__(self, sys_clk_freq, data_timeout):

# # #

if with_data_buffer:
assert source is self.source
self.data_buffer = stream.Buffer([("data", 8), ("status", 3)], pipe_valid=True, pipe_ready=True)
self.comb += self.data_buffer.source.connect(self.source)
source = self.data_buffer.sink
assert source is not self.source

timeout = Signal(32, reset=int(data_timeout*sys_clk_freq))
count = Signal(10)

Expand Down

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