RFC: phy: add support for Lattice ECP5 (SDPHYIOECP5) #10
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per @daveshah1, it might be that the ECP5 ODDRX1F has a 3 clock cycle latency, which might be higher than the 1 or 2 cycle latency on the Xilinx, which might be a breaking change. I wanted to write that down here, to remember when I (or anyone else) end up working on this later... |
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Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
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@gsomlo: i'm merging it since i'm going to work on it and will also do some cleanup on the PHYs so want to avoid merge conflicts. |
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The latency was indeed too high and was causing de-synchronization between CLK and CMD/DAT. I merged and replaced the ECP5 PHY with a Generic PHY in 27572e7 and tested it successfully on the ULX3S target of LiteX with:
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@enjoy-digital: please don't apply (yet) -- this "should" (but isn't) working at the moment, so let's wait until we figure it out :)