Merge pull request #22 from rohitk-singh/regression-fix

Review: Regression Fix for 7-series HDMI Input and Output
litex-hub · Jan 29, 2019 · 98e145f · 98e145f
2 parents 0993a4e + 411669b
commit 98e145f
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Showing 3 changed files with 16 additions and 9 deletions.
diff --git a/litevideo/input/clocking.py b/litevideo/input/clocking.py
@@ -101,16 +101,16 @@ def __init__(self, pads, clkin_freq=148.5e6, split_clocking=False):
 
         self.locked = Signal()
         self.clock_domains.cd_pix = ClockDomain()
+        self.clock_domains.cd_pix_o = ClockDomain()
         self.clock_domains.cd_pix1p25x = ClockDomain()
         self.clock_domains.cd_pix5x = ClockDomain(reset_less=True)
+        self.clock_domains.cd_pix5x_o = ClockDomain(reset_less=True)
 
         if split_clocking:
             self._mmcm_write_o = CSR()
             self._mmcm_read_o = CSR()
             self._mmcm_dat_o_r = CSRStatus(16)
             self._mmcm_drdy_o = CSRStatus()
-            self.clock_domains.cd_pix_o = ClockDomain()
-            self.clock_domains.cd_pix5x_o = ClockDomain(reset_less=True)
 
         # # #
 
@@ -218,6 +218,11 @@ def __init__(self, pads, clkin_freq=148.5e6, split_clocking=False):
                     self._mmcm_drdy_o.status.eq(1)
                 )
             ]
+        else:
+            self.comb += [
+                self.cd_pix_o.clk.eq(self.cd_pix.clk),
+                self.cd_pix5x_o.clk.eq(self.cd_pix5x.clk)
+            ]
 
         self.specials += MultiReg(mmcm_locked, self.locked, "sys")
         self.comb += self._locked.status.eq(self.locked)
@@ -229,4 +234,6 @@ def __init__(self, pads, clkin_freq=148.5e6, split_clocking=False):
 
         if split_clocking:
             self.specials += AsyncResetSynchronizer(self.cd_pix_o, ~mmcm_locked_o)
+        else:
+            self.comb += self.cd_pix_o.rst.eq(self.cd_pix.rst)
 
diff --git a/litevideo/output/driver.py b/litevideo/output/driver.py
@@ -60,4 +60,4 @@ def __init__(self, device, pads, mode, external_clocking=None):
             self.submodules.hdmi_phy = hdmi_phy_cls[family](pads, mode)
             if hasattr(self.hdmi_phy, "serdesstrobe"):
                 self.comb += self.hdmi_phy.serdesstrobe.eq(self.clocking.serdesstrobe)
-                self.comb += sink.connect(self.hdmi_phy.sink)
+            self.comb += sink.connect(self.hdmi_phy.sink)
diff --git a/litevideo/output/hdmi/s7.py b/litevideo/output/hdmi/s7.py
@@ -12,7 +12,7 @@
 class S7HDMIOutEncoderSerializer(Module):
     def __init__(self, pad_p, pad_n, bypass_encoder=False):
         if not bypass_encoder:
-            self.submodules.encoder = ClockDomainsRenamer("pix_o")(Encoder())
+            self.submodules.encoder = ClockDomainsRenamer("pix")(Encoder())
             self.d, self.c, self.de = self.encoder.d, self.encoder.c, self.encoder.de
             self.data = self.encoder.out
         else:
@@ -27,7 +27,7 @@ def __init__(self, pad_p, pad_n, bypass_encoder=False):
             self.comb += data.eq(self.data)
 
         ce = Signal()
-        self.sync.pix_o += ce.eq(~ResetSignal("pix_o"))
+        self.sync.pix += ce.eq(~ResetSignal("pix"))
 
         shift = Signal(2)
         pad_se = Signal()
@@ -42,8 +42,8 @@ def __init__(self, pad_p, pad_n, bypass_encoder=False):
                 o_OQ=pad_se,
                 i_OCE=ce,
                 i_TCE=0,
-                i_RST=ResetSignal("pix_o"),
-                i_CLK=ClockSignal("pix5x_o"), i_CLKDIV=ClockSignal("pix_o"),
+                i_RST=ResetSignal("pix"),
+                i_CLK=ClockSignal("pix5x"), i_CLKDIV=ClockSignal("pix"),
                 i_D1=data[0], i_D2=data[1],
                 i_D3=data[2], i_D4=data[3],
                 i_D5=data[4], i_D6=data[5],
@@ -59,8 +59,8 @@ def __init__(self, pad_p, pad_n, bypass_encoder=False):
 
                 i_OCE=ce,
                 i_TCE=0,
-                i_RST=ResetSignal("pix_o"),
-                i_CLK=ClockSignal("pix5x_o"), i_CLKDIV=ClockSignal("pix_o"),
+                i_RST=ResetSignal("pix"),
+                i_CLK=ClockSignal("pix5x"), i_CLKDIV=ClockSignal("pix"),
                 i_D1=0, i_D2=0,
                 i_D3=data[8], i_D4=data[9],
                 i_D5=0, i_D6=0,