wishbone/wishbone2csr: use wishbone.sel on CSR write.

CSR write is only done if wishbone.sel != 0. This should avoid the need for 64-bit
CSR alignment on 64-bit CPUs since a 64-bit Wishbone write access targeting only the
32-bit LSB or MSB will be splitted in 2x32-bit accesses: one with sel=0xf, one with sel=0.

litex/soc/interconnect/wishbone.py

@@ -387,7 +387,7 @@ def __init__(self, bus_wishbone=None, bus_csr=None):
         fsm.act("WRITE-READ",
             If(self.wishbone.cyc & self.wishbone.stb,
                 self.csr.adr.eq(self.wishbone.adr),
-                self.csr.we.eq(self.wishbone.we),
+                self.csr.we.eq(self.wishbone.we & (self.wishbone.sel != 0)),
                 NextState("ACK")
             )
         )