integration/soc/add_uartbone: fix jtag_uart integration.

litex/soc/integration/soc.py

@@ -1163,16 +1163,15 @@ def add_uart(self, name, baudrate=115200, fifo_depth=16):
     # Add UARTbone ---------------------------------------------------------------------------------
     def add_uartbone(self, name="serial", clk_freq=None, baudrate=115200, cd="sys"):
         from litex.soc.cores import uart
+        if clk_freq is None:
+            clk_freq = self.sys_clk_freq
         if name == "jtag_uart":
             from litex.soc.cores.jtag import JTAGPHY
             phy = JTAGPHY(device=self.platform.device)
         else:
-            phy = uart.UARTPHY(platform.request(name), clk_freq, bandrate)
+            phy = uart.UARTPHY(self.platform.request(name), clk_freq, baudrate)
         self.submodules += phy
-        self.submodules.uartbone = uart.UARTBone(
-            phy      = phy,
-            clk_freq = clk_freq if clk_freq is not None else self.sys_clk_freq,
-            cd       = cd)
+        self.submodules.uartbone = uart.UARTBone(phy=phy, clk_freq=clk_freq, cd=cd)
         self.bus.add_master(name="uartbone", master=self.uartbone.wishbone)
 
     # Add SDRAM ------------------------------------------------------------------------------------