Change vexriscv submodule to Antmicro's fork

enjoy-digital · Mar 6, 2019 · d54a8eb · d54a8eb
1 parent c644c4c
commit d54a8eb
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diff --git a/.gitmodules b/.gitmodules
@@ -15,4 +15,4 @@
 	url = https://github.com/enjoy-digital/tapcfg
 [submodule "litex/soc/cores/cpu/vexriscv/verilog"]
 	path = litex/soc/cores/cpu/vexriscv/verilog
-	url = https://github.com/m-labs/VexRiscv-verilog.git
+	url = https://github.com/antmicro/VexRiscv-verilog.git
diff --git a/litex/soc/cores/cpu/vexriscv/verilog b/litex/soc/cores/cpu/vexriscv/verilog