regression: memtest fails on nexys4ddr SoC startup

[gsomlo]

I'm using the script below to build a vexriscv variant of litex/boards/targets/nexys4ddr.py, and it works with commit dad7b29, but breaks with "Memtest bus failed 128/256 errors, Memtest data failed: 524288/524288 errors" if I build the current master (2ebfab5). Here's my build script:

rm -rf ~/.local/bin ~/.local/lib ~/LITEX
mkdir ~/LITEX; cd ~/LITEX
# grab litex & friends (only litex has submodules, but --recursive won't hurt):
PRJ='x dram eth usb pcie sdcard iclink video scope'
for i in $PRJ; do
  git clone --recursive https://github.com/enjoy-digital/lite$i
done

# FIXME: Memtest fails, this rollback fixes it:
(cd litex;    git checkout dad7b292)

# "install" to local user's ~/.local/[usr|bin]:
for i in $PRJ; do
  (cd lite$i; python3 setup.py develop --user)
done

# build nexys4ddr full SoC example (using vexriscv cpu, and custom vivado path):
sed -i '/^\( *\)integrated_sram_size.*$/s//&\n\1cpu_type="vexriscv",/' \
  litex/litex/boards/targets/nexys4ddr.py
sed -i '/builder.build/s|()|(toolchain_path="/home/somlo/Xilinx/Vivado")|' \
  litex/litex/boards/targets/nexys4ddr.py
litex/litex/boards/targets/nexys4ddr.py

EDIT: after a bisect, the culprit appears to be commit 3dd529e ("add ECP5 support") -- something about the modified #defines in sdram.c disagrees with the proper operation of the nexys4ddr DDR2 controller.

[gsomlo]

fixed by commit 317dba8 -- thanks!