Add optional support for fixed CSR mapping.

[enjoy-digital]

By default, location is still automatically determined but it's now possible to
specific locations:

The following module:

class MyModule(Module, AutoCSR):
    def __init__(self):
        self.csr0 = CSRStorage()
        self.csr1 = CSRStorage(n=0)
        self.csr2 = CSRStorage(n=2)

built on a SoC with 32-bit CSR data-width will have the following CSR mapping:

- 0x00 : csr1
- 0x04 : csr0
- 0x08 : reserved
- 0x0c : csr2

[gsomlo]

After this PR was applied I'm getting an error building litex-rocket with the following command line:

litex-boards/litex_boards/targets/digilent_nexys_video.py --build \
    --cpu-type rocket --cpu-variant full4d --sys-clk-freq 50e6 \
    --with-ethernet --with-sdcard \
    --with-sata --sata-gen 1 --with-sata-pll-refclk

The error is:

...
INFO:SoCCSRHandler:ddrphy CSR allocated at Location 1.
Traceback (most recent call last):
  File "/home/somlo/LITEX/litex-boards/litex_boards/targets/digilent_nexys_video.py", line 211, in <module>
    main()
  File "/home/somlo/LITEX/litex-boards/litex_boards/targets/digilent_nexys_video.py", line 204, in main
    builder.build(**builder_kwargs)
  File "/home/somlo/LITEX/litex/litex/soc/integration/builder.py", line 329, in build
    self.soc.finalize()
  File "/home/somlo/LITEX/litex/litex/soc/integration/soc.py", line 1193, in finalize
    self.submodules.csr_bankarray = csr_bus.CSRBankArray(self,
  File "/home/somlo/LITEX/litex/litex/soc/interconnect/csr_bus.py", line 215, in __init__
    self.scan(ifargs, ifkwargs)
  File "/home/somlo/LITEX/litex/litex/soc/interconnect/csr_bus.py", line 229, in scan
    csrs = obj.get_csrs(sort=True)
TypeError: LiteEthMAC.get_csrs() got an unexpected keyword argument 'sort'

[enjoy-digital]

Thanks @gsomlo for the feedback, 76d3a77 should fix it.

[gsomlo]

@enjoy-digital -- while the individual base addresses are the same as before, this change shuffled the registers within the ethmac set:

$ diff csr_nexys_video.csv csr.csv 
2c2
< # Auto-generated by LiteX (2de9bb20) on 2022-10-21 10:32:16
---
> # Auto-generated by LiteX (fd285b17) on 2022-10-21 17:17:26
39,52c39,52
< csr_register,ethmac_sram_writer_slot,0x12001000,1,ro
< csr_register,ethmac_sram_writer_length,0x12001004,1,ro
< csr_register,ethmac_sram_writer_errors,0x12001008,1,ro
< csr_register,ethmac_sram_writer_ev_status,0x1200100c,1,ro
< csr_register,ethmac_sram_writer_ev_pending,0x12001010,1,rw
< csr_register,ethmac_sram_writer_ev_enable,0x12001014,1,rw
< csr_register,ethmac_sram_reader_start,0x12001018,1,rw
< csr_register,ethmac_sram_reader_ready,0x1200101c,1,ro
< csr_register,ethmac_sram_reader_level,0x12001020,1,ro
< csr_register,ethmac_sram_reader_slot,0x12001024,1,rw
< csr_register,ethmac_sram_reader_length,0x12001028,1,rw
< csr_register,ethmac_sram_reader_ev_status,0x1200102c,1,ro
< csr_register,ethmac_sram_reader_ev_pending,0x12001030,1,rw
< csr_register,ethmac_sram_reader_ev_enable,0x12001034,1,rw
---
> csr_register,ethmac_sram_reader_length,0x12001000,1,rw
> csr_register,ethmac_sram_reader_level,0x12001004,1,ro
> csr_register,ethmac_sram_reader_ready,0x12001008,1,ro
> csr_register,ethmac_sram_reader_slot,0x1200100c,1,rw
> csr_register,ethmac_sram_reader_start,0x12001010,1,rw
> csr_register,ethmac_sram_reader_ev_enable,0x12001014,1,rw
> csr_register,ethmac_sram_reader_ev_pending,0x12001018,1,rw
> csr_register,ethmac_sram_reader_ev_status,0x1200101c,1,ro
> csr_register,ethmac_sram_writer_errors,0x12001020,1,ro
> csr_register,ethmac_sram_writer_length,0x12001024,1,ro
> csr_register,ethmac_sram_writer_slot,0x12001028,1,ro
> csr_register,ethmac_sram_writer_ev_enable,0x1200102c,1,rw
> csr_register,ethmac_sram_writer_ev_pending,0x12001030,1,rw
> csr_register,ethmac_sram_writer_ev_status,0x12001034,1,ro
54,55c54,55
< csr_register,ethmac_rx_datapath_preamble_errors,0x1200103c,1,ro
< csr_register,ethmac_rx_datapath_crc_errors,0x12001040,1,ro
---
> csr_register,ethmac_rx_datapath_crc_errors,0x1200103c,1,ro
> csr_register,ethmac_rx_datapath_preamble_errors,0x12001040,1,ro

This breaks the LiteETH linux driver authored by @shenki . Most linux drivers for LiteX peripherals can tolerate the base address changing (via dts/dtb), but a shuffle of the registers within a set like the above breaks the driver, which until now has relied on hard-coding the register offsets and sizes, see https://github.com/torvalds/linux/blob/master/drivers/net/ethernet/litex/litex_liteeth.c#L16-L32

Unless we can try to keep the registers within a given peripheral in a constant and predictable order, we should brainstorm ways to pass individual offsets into Linux somehow (not sure DTS/DTB is designed for such levels of granularity, though).

Interestingly enough, it's only LiteETH that's affected at this time, all other devices' registers remain unshuffled for now...

[enjoy-digital]

Hi @gsomlo,

sorry for this, ironically the aim of these changes is to do the opposite and allow fixed CSR mapping :) That's just that LiteETH CSR collection is done differently (through a custom get_csrs) and I probably screwed up :(

I'll fix this.

[enjoy-digital]

With 88d8977 I now get the same mapping with your command.