cpu/vexiiriscv integration

litex/soc/cores/cpu/naxriscv/core.py

@@ -294,7 +294,11 @@ def generate_netlist_name(reset_address):
 
 
     @staticmethod
-    def git_setup(name, dir, repo, branch, hash):
+    def git_setup(name, dir, repo, branch, hash, update):
+        if update == "no":
+            return
+        if "recommended" not in update:
+            hash = ""
         if not os.path.exists(dir):
             # Clone Repo.
             print(f"Cloning {name} Git repository...")
@@ -306,7 +310,7 @@ def git_setup(name, dir, repo, branch, hash):
         print(f"Updating {name} Git repository...")
         cwd = os.getcwd()
         os.chdir(os.path.join(dir))
-        wipe_cmd = "&& git clean --force -d -x && git reset --hard" if "wipe" in NaxRiscv.update_repo else ""
+        wipe_cmd = "&& git clean --force -d -x && git reset --hard" if "wipe" in update else ""
         checkout_cmd = f"&& git checkout {hash}" if hash is not None else ""
         subprocess.check_call(f"cd {dir} {wipe_cmd} && git checkout {branch} && git submodule init && git pull --recurse-submodules {checkout_cmd}", shell=True)
         os.chdir(cwd)
@@ -318,8 +322,7 @@ def generate_netlist(reset_address):
         ndir = os.path.join(vdir, "ext", "NaxRiscv")
         sdir = os.path.join(vdir, "ext", "SpinalHDL")
 
-        if NaxRiscv.update_repo != "no":
-            NaxRiscv.git_setup("NaxRiscv", ndir, "https://github.com/SpinalHDL/NaxRiscv.git", "main", "f3357383" if NaxRiscv.update_repo=="recommended" else None)
+        NaxRiscv.git_setup("NaxRiscv", ndir, "https://github.com/SpinalHDL/NaxRiscv.git", "main", "f3357383", NaxRiscv.update_repo)
 
         gen_args = []
         gen_args.append(f"--netlist-name={NaxRiscv.netlist_name}")
@@ -399,13 +402,13 @@ def add_soc_components(self, soc):
 
         if NaxRiscv.jtag_tap:
             self.jtag_tms = Signal()
-            self.jtag_tck = Signal()
+            self.jtag_clk = Signal()
             self.jtag_tdi = Signal()
             self.jtag_tdo = Signal()
 
             self.cpu_params.update(
                 i_jtag_tms = self.jtag_tms,
-                i_jtag_tck = self.jtag_tck,
+                i_jtag_tck = self.jtag_clk,
                 i_jtag_tdi = self.jtag_tdi,
                 o_jtag_tdo = self.jtag_tdo,
             )
@@ -452,7 +455,10 @@ def add_soc_components(self, soc):
             # Reset SoC's CRG when debug_ndmreset rising edge.
             self.sync.debug_por += debug_ndmreset_last.eq(debug_ndmreset)
             self.comb += debug_ndmreset_rise.eq(debug_ndmreset & ~debug_ndmreset_last)
-            self.comb += If(debug_ndmreset_rise, soc.crg.rst.eq(1))
+            if soc.get_build_name() == "sim":
+                self.comb += If(debug_ndmreset_rise, soc.crg.cd_sys.rst.eq(1))
+            else:
+                self.comb += If(debug_ndmreset_rise, soc.crg.rst.eq(1))
 
         self.soc_bus = soc.bus # FIXME: Save SoC Bus instance to retrieve the final mem layout on finalization.
 
@@ -470,6 +476,16 @@ def add_memory_buses(self, address_width, data_width):
         )
         self.memory_buses.append(mbus)
 
+        self.comb += mbus.aw.cache.eq(0xF)
+        self.comb += mbus.aw.lock.eq(0)
+        self.comb += mbus.aw.prot.eq(1)
+        self.comb += mbus.aw.qos.eq(0)
+
+        self.comb += mbus.ar.cache.eq(0xF)
+        self.comb += mbus.ar.lock.eq(0)
+        self.comb += mbus.ar.prot.eq(1)
+        self.comb += mbus.ar.qos.eq(0)
+
         self.cpu_params.update(
             # Memory Bus (Master).
             # --------------------

litex/soc/cores/cpu/vexiiriscv/__init__.py

@@ -0,0 +1 @@
+from litex.soc.cores.cpu.vexiiriscv.core  import VexiiRiscv

litex/soc/cores/cpu/vexiiriscv/boot-helper.S

@@ -0,0 +1,15 @@
+.section    .text, "ax", @progbits
+.global boot_helper
+.global smp_lottery_target
+.global smp_lottery_lock
+.global smp_lottery_args
+
+boot_helper:
+	sw x10, smp_lottery_args  , x14
+	sw x11, smp_lottery_args+4, x14
+	sw x12, smp_lottery_args+8, x14
+	sw x13, smp_lottery_target, x14
+	fence w, w
+	li x15, 1
+	sw x15, smp_lottery_lock, x14
+	jr x13