Hard core CPUs

LiteX currently has minimal support (compiling and running BIOS, with UART serial terminal, connected to CSR bus in gateware) on these following hard ARM CPUs: Xilinx Zynq-7000, Xilinx UltraScale+ MPSoC, QuickLogic EOS S3, Gowin EMCU.

Note: producing working gateware on all these except Gowin EMCU currently requires patching LiteX locally in some way to remove address decoding on the CSR bus.

Xilinx Zynq-7000

Demonstrated on Digilent Zedboard. As any complete workflow on Zynq devices requires a number of tools, scripts and build steps besides software and gateware binaries built by LiteX to produce and program boot images - refer to this repository for a complete implementation and details. Serial terminal is on the USB-UART.

Xilinx UltraScale+ MPSoC

Demonstrated on Xilinx KV260. Refer to the readme in this repository for a workflow allowing execution via JTAG. Serial terminal is on the USB-UART.

QuickLogic EOS S3

Demonstrated on QuickLogic QuickFeather. Use python lib/litex-boards/litex_boards/targets/quicklogic_quickfeather.py --build with path to QORC SDK provided in QORC_SDK environment variable to implement - refer to this repository for an example. Serial terminal is on pins J3.2/J3.3.

Note: producing a working gateware currently requires patching LiteX locally in some way to remove address decoding on the CSR bus.

Gowin EMCU

Demonstrated on Sipeed Tang Nano 4K. To implement use python litex-boards/litex_boards/targets/sipeed_tang_nano_4k.py --cpu-type=gowin_emcu --build. Program with Gowin Programmer in MCU mode using project.fs and bios.bin. Look at the platform file for the locations of the serial terminal pins.