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                         Migen inside

                Build your hardware, easily!
              Copyright 2012-2019 / EnjoyDigital

Welcome to LiteX wiki!

LiteX is a FPGA design/SoC builder that can be used to build cores, create SoCs and full FPGA designs.

LiteX is based on Migen and provides specific building/debugging tools for a higher level of abstraction and compatibily with the LiteX core ecosystem.

Think of Migen as a toolbox to create FPGA designs in Python and LiteX as a SoC builder to create/develop/debug FPGA SoCs in Python.

Typical LiteX design flow:

                        +---------------+
                        |FPGA toolchains|
                        +----^-----+----+
                             |     |
                          +--+-----v--+
         +-------+        |           |
         | Migen +-------->           |
         +-------+        |           |        Your design
                          |   LiteX   +---> ready to be used!
                          |           |
+----------------------+  |           |
|LiteX Cores Ecosystem +-->           |
+----------------------+  +-^-------^-+
 (Eth, SATA, DRAM, USB,     |       |
  PCIe, Video, etc...)      +       +
                           board   target
                           file    file

LiteX already supports various softcores CPUs: LM32, Mor1kx, PicoRV32, VexRiscv and is compatible with the LiteX's Cores Ecosystem:

Name	Build Status	Description	Supported Standards	Supported Hardware
LiteDRAM		Dynamic RAM controller	SDRAM, DDR, LPDDR, DDR2, DDR3, DDR4	Generic Verilog, Xilinx Spartan 6 + 7 Series + Ultrascale, Lattice ECP5
LiteEth		Ethernet	100, 1000 Mbit, MII, GMII & RGMII and many high speed tranceivers	Generic Verilog, Xilinx Spartan 6 + 7 Series + Ultrascale, Lattice ECP5
LitePCIe		PCIe	Gen1, Gen2, x1, x2 x4	Xilinx 7‑series, Intel Cyclone V, and soon Lattice ECP5
LiteSATA		SATA	1.5/3.0/6.0 GBps	Xilinx 7‑series
LiteUSB		USB transfer
LiteSDCard		SD card	SD / SDHC / SDXC / SDUC, Default Speed, High Speed, UHS-I	Xilinx Spartan 6 + 7 Series
LiteICLink		Inter-Chip communication	Custom protocol over Single Ended or LVDS Pair	Xilinx 7‑series + Ultrascale
LiteJESD204B		JESD204B		Xilinx 7‑series + Ultrascale
LiteVideo		DVI, HDMI	DVI, HDMI	Xilinx Spartan 6 + 7‑series
LiteScope		Embedded FPGA logic analyzer	PCIe, UART, Ethernet	Generic Verilog