update E40X to include bit manipulation 1.0.0

eroom1966 · Oct 26, 2021 · c437c42 · c437c42
1 parent c8a3883
commit c437c42
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Showing 6 changed files with 3 additions and 3 deletions.
diff --git a/cv32e40x/tests/cfg/default.yaml b/cv32e40x/tests/cfg/default.yaml
@@ -2,7 +2,7 @@ name: default
 description: Default configuration for CV32E40X simulations
 compile_flags:
 ovpsim: >
-#    --showoverrides
+    --verbose --showoverrides
 #    --trace --tracechange --traceshowicount --monitornets
 cflags: >
 
diff --git a/vendor_lib/imperas/imperas_DV_COREV/README.md b/vendor_lib/imperas/imperas_DV_COREV/README.md
@@ -4,8 +4,8 @@ A Complete, Fully Functional, Configurable CV32E40P Simulation Model
 ===
 
 Author: Imperas Software, Ltd., using OVP Open Standard APIs  
-Date   : 20211025 
-Version: 20200821.430  
+Date   : 20211026 
+Version: 20200821.431  
 License: Simulation Model CV32E40P licensed under [Software License Agreement for Open Virtual Platforms Technology](OVP_IMPERAS_LICENSE.pdf)
 RISC-V Specifications currently supported:
 - RISC-V Instruction Set Manual, Volume I: User-Level ISA (User Architecture Version 2.3)

diff --git a/vendor_lib/imperas/imperas_DV_COREV/bin/Linux64/imperas_CV32.dpi.so b/vendor_lib/imperas/imperas_DV_COREV/bin/Linux64/imperas_CV32.dpi.so
diff --git a/...mperas/imperas_DV_COREV/doc/OVP_Model_Specific_Information_openhwgroup_riscv_CV32E40P.pdf b/...mperas/imperas_DV_COREV/doc/OVP_Model_Specific_Information_openhwgroup_riscv_CV32E40P.pdf
diff --git a/...mperas/imperas_DV_COREV/doc/OVP_Model_Specific_Information_openhwgroup_riscv_CV32E40S.pdf b/...mperas/imperas_DV_COREV/doc/OVP_Model_Specific_Information_openhwgroup_riscv_CV32E40S.pdf
diff --git a/...mperas/imperas_DV_COREV/doc/OVP_Model_Specific_Information_openhwgroup_riscv_CV32E40X.pdf b/...mperas/imperas_DV_COREV/doc/OVP_Model_Specific_Information_openhwgroup_riscv_CV32E40X.pdf