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Verilog program for FPGA for 8bit computer inspired from RISC-V architecture

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Name		Name	Last commit message	Last commit date
Latest commit History 4 Commits
constraints		constraints
src		src
tb		tb
test		test
vcd		vcd
.gitignore		.gitignore
ReadME.md		ReadME.md
risc-me.gprj		risc-me.gprj
schematic.pdf		schematic.pdf

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risc-me

For tb generator

iverilog -o ./tb/alu_tb ./src/alu.v ./test/alu_tb.v -I ./src

For vcd generator

vvp ./tb/alu_tb -o ./vcd

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Verilog program for FPGA for 8bit computer inspired from RISC-V architecture

risc-v risc-v-assembly

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