I2C default ISR resets with Cache disabled but cached memory region accessed (IDFGH-8835)

[hornbartho]

Answers checklist.

• I have read the documentation ESP-IDF Programming Guide and the issue is not addressed there.
• I have updated my IDF branch (master or release) to the latest version and checked that the issue is present there.
• I have searched the issue tracker for a similar issue and not found a similar issue.

General issue report

Hi Folks,

I am pretty new to ESP, so sorry if this is a stupid question.

I am trying to implement the I2C interrupt from IRAM, but I am getting the following error when I activate the ESP_INTR_FLAG_IRAM flag: Guru Meditation Error: Core 0 panic'ed (Cache disabled but cached memory region accessed).

From what I understand is that this is caused by not all of the required code being saved to IRAM/DRAM and then the system tries to access it in cache, but the flash is being used for another function.

I am running Espressif with IDF version v4.4.3 and please see my config file attached. Please can someone give me an idea of how I can get the I2C to run on IRAM? Since from other posts, it seems like this issue has been solved: [https://github.com//issues/8422]

sdkconfig.txt

[AxelLin]

#10079 (comment)