I2C default ISR resets with Cache disabled but cached memory region accessed (IDFGH-6795) #8422
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diff --git a/components/driver/i2c.c b/components/driver/i2c.c
index 438d1efc12..3637288596 100644
--- a/components/driver/i2c.c
+++ b/components/driver/i2c.c
@@ -1366,7 +1366,7 @@ static void IRAM_ATTR i2c_master_cmd_begin_static(i2c_port_t i2c_num)
break;
}
}
- i2c_hal_update_config(&(i2c_context[i2c_num].hal));
+ i2c_hal_update_config_isr(&(i2c_context[i2c_num].hal));
i2c_hal_trans_start(&(i2c_context[i2c_num].hal));
return;
}
diff --git a/components/esptool_py/esptool b/components/esptool_py/esptool
--- a/components/esptool_py/esptool
+++ b/components/esptool_py/esptool
@@ -1 +1 @@
-Subproject commit b082b0ed2d86b3330134c4854a021dfd14c29b08
+Subproject commit b082b0ed2d86b3330134c4854a021dfd14c29b08-dirty
diff --git a/components/hal/include/hal/i2c_hal.h b/components/hal/include/hal/i2c_hal.h
index b255878cc4..698d0da5d8 100644
--- a/components/hal/include/hal/i2c_hal.h
+++ b/components/hal/include/hal/i2c_hal.h
@@ -91,6 +91,7 @@ typedef struct {
* @return None
*/
#define i2c_hal_enable_master_tx_it(hal) i2c_ll_master_enable_tx_it((hal)->dev)
+#define i2c_hal_update_config_isr(hal) i2c_ll_update((hal)->dev)
/**
* @brief Clear I2C slave TX interrupt |
|
Hi @HassanSaied Thanks for reporting this issue, and bringing up this fix. We will look into this issue more detailedly to find out all the wrong cases. This kind of issues are a bit hard to fix completely, because the inline logic is somehow determined by the compiler behavior under different configs... Before that, you can work with your fix, or try add FORCE_INLINE_ATTR to the |
espressif-bot
added
Resolution: NA
|
@ginkgm |
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Environment
git describe --tagsto find it):v4.4-rc1-8-g0b46ac1732
xtensa-esp32-elf-gcc --versionto find it):xtensa-esp32-elf-gcc (crosstool-NG esp-2021r2) 8.4.0
Problem Description
When setting the I2C interrupt to ESP_INTR_FLAG_IRAM in the i2c_driver_install, the I2C interrupt will reset the system with a cache disabled error when accessing the SPIFFS at the same time the I2C module is reading data from a slave
Expected Behavior
System doesn't reset when using an ISR allocated in IRAM while cache is disabled
Actual Behavior
System resets
Steps to reproduce
Debug Logs
The core dump for the same reset shows a slightly different story, but a much more concise one as i2c_hal_enable_slave_rx_it should never be called, as my I2C is in master mode
Other items if possible
I did some investigation and I found that the issue is that the function i2c_hal_update_config which is called in i2c_master_cmd_begin_static is not defined with IRAM_ATTR, and it seems to cause the error, because when I comment it every thing works fine.
On my ESP32 this function seems to do nothing, but I think it is necessary for other platforms.
A proposed fix would be to skip the i2c_hal_update_config and directly call the lower layer i2c_ll_update (which is already inline so would pose no problems) via a macro. This fix is in the included patch
buildfolder (note this may contain all the code details and symbols of your project.)I2CIssue.zip
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