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Enable IO20 on ESP32 (IDFGH-5140) #6918

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Enable IO20 on ESP32 (IDFGH-5140) #6918

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2 changes: 1 addition & 1 deletion components/soc/esp32/gpio_periph.c
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Original file line number Diff line number Diff line change
Expand Up @@ -35,7 +35,7 @@ const uint32_t GPIO_PIN_MUX_REG[SOC_GPIO_PIN_COUNT] = {
IO_MUX_GPIO17_REG,
IO_MUX_GPIO18_REG,
IO_MUX_GPIO19_REG,
0,
IO_MUX_GPIO20_REG,
IO_MUX_GPIO21_REG,
IO_MUX_GPIO22_REG,
IO_MUX_GPIO23_REG,
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2 changes: 1 addition & 1 deletion components/soc/esp32/include/soc/soc_caps.h
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Original file line number Diff line number Diff line change
Expand Up @@ -116,7 +116,7 @@
// control pullup/down/capability, independent with RTC registers.

// 0~39 except from 20, 24, 28~31 are valid
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May want to update the comment here to reflect the change made below -

Suggested change
// 0~39 except from 20, 24, 28~31 are valid
// 0~39 except for 24, 28~31 are valid

#define SOC_GPIO_VALID_GPIO_MASK (0xFFFFFFFFFFULL & ~(0ULL | BIT20 | BIT24 | BIT28 | BIT29 | BIT30 | BIT31))
#define SOC_GPIO_VALID_GPIO_MASK (0xFFFFFFFFFFULL & ~(0ULL | BIT24 | BIT28 | BIT29 | BIT30 | BIT31))
// GPIO >= 34 are input only
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK (SOC_GPIO_VALID_GPIO_MASK & ~(0ULL | BIT34 | BIT35 | BIT36 | BIT37 | BIT38 | BIT39))

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