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Fix DTLB BlockRAM ports integration with LM32 pipeline signaling

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commit c73e8e802bd6d79299f737777b828ccc1e32aa1c 1 parent 782d144
@fallen authored
Showing with 2 additions and 2 deletions.
  1. +2 −2 cores/lm32/rtl/lm32_dcache.v
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4 cores/lm32/rtl/lm32_dcache.v
@@ -551,8 +551,8 @@ assign dtlb_tag_write_address = (dtlb_flushing == `TRUE)
? dtlb_flush_set
: dtlb_update_vaddr_csr_reg[`LM32_DTLB_IDX_RNG];
-assign dtlb_data_read_port_enable = (stall_x == `FALSE);
-assign dtlb_tag_read_port_enable = (stall_x == `FALSE);
+assign dtlb_data_read_port_enable = (stall_x == `FALSE) || !stall_m;
+assign dtlb_tag_read_port_enable = (stall_x == `FALSE) || !stall_m;
assign dtlb_write_port_enable = dtlb_updating || dtlb_flushing;
assign dtlb_write_tag = (dtlb_flushing == `TRUE)
? `LM32_DTLB_INVALID_TAG
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