Fix DTLB BlockRAM ports integration with LM32 pipeline signaling

fallen · Apr 12, 2012 · c73e8e8 · c73e8e8
1 parent 782d144
commit c73e8e8
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/cores/lm32/rtl/lm32_dcache.v b/cores/lm32/rtl/lm32_dcache.v
@@ -551,8 +551,8 @@ assign dtlb_tag_write_address = (dtlb_flushing == `TRUE)
 				? dtlb_flush_set
 				: dtlb_update_vaddr_csr_reg[`LM32_DTLB_IDX_RNG];
 
-assign dtlb_data_read_port_enable = (stall_x == `FALSE);
-assign dtlb_tag_read_port_enable = (stall_x == `FALSE);
+assign dtlb_data_read_port_enable = (stall_x == `FALSE) || !stall_m;
+assign dtlb_tag_read_port_enable = (stall_x == `FALSE) || !stall_m;
 assign dtlb_write_port_enable = dtlb_updating || dtlb_flushing;
 assign dtlb_write_tag = (dtlb_flushing == `TRUE)
 			? `LM32_DTLB_INVALID_TAG