Name		Name	Last commit message	Last commit date
Latest commit History 3 Commits
simulation/modelsim		simulation/modelsim
171044009.qar		171044009.qar
README.md		README.md
adder.v		adder.v
adder_testbench.v		adder_testbench.v
alu.v		alu.v
alu_control.v		alu_control.v
alu_control_testbench.v		alu_control_testbench.v
alu_testbench.v		alu_testbench.v
and_gates.v		and_gates.v
comparator.v		comparator.v
comparator_testbench.v		comparator_testbench.v
control_unit.v		control_unit.v
control_unit_testbench.v		control_unit_testbench.v
instruction_memory.v		instruction_memory.v
load_upper_16.v		load_upper_16.v
mips32.v		mips32.v
mips32_testbench.v		mips32_testbench.v
mips_data_memory.v		mips_data_memory.v
mips_registers.v		mips_registers.v
mux_2_to_1.v		mux_2_to_1.v
mux_2_to_1_testbench.v		mux_2_to_1_testbench.v
new_get_rd.v		new_get_rd.v
new_get_rd_testbench.v		new_get_rd_testbench.v
not_gates.v		not_gates.v
or_gates.v		or_gates.v
register.v		register.v
shift_left_2.v		shift_left_2.v
shift_left_2_testbench.v		shift_left_2_testbench.v
sign_extend.v		sign_extend.v
sign_extend_testbench.v		sign_extend_testbench.v
xor_gates.v		xor_gates.v

Provide feedback

Saved searches